| Commit message (Expand) | Author | Age | Files | Lines |
* | clk: meson: axg: mark fdiv2 and fdiv3 as critical | Jerome Brunet | 2018-11-08 | 1 | -0/+13 |
* | clk: meson-axg: pcie: drop the mpll3 clock parent | Yixun Lan | 2018-09-26 | 1 | -2/+4 |
* | clk: meson: clk-pll: drop hard-coded rates from pll tables | Jerome Brunet | 2018-09-26 | 1 | -37/+36 |
* | clk: meson: clk-pll: remove od parameters | Jerome Brunet | 2018-09-26 | 1 | -130/+154 |
* | clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary | Jerome Brunet | 2018-09-26 | 1 | -1/+0 |
* | clk: meson: clk-pll: add enable bit | Jerome Brunet | 2018-09-26 | 1 | -3/+25 |
* | clk: meson: add gen_clk | Jerome Brunet | 2018-07-09 | 1 | -1/+63 |
* | clk: meson-axg: add clocks required by pcie driver | Yixun Lan | 2018-07-09 | 1 | -0/+145 |
* | clk: meson: remove obsolete register access | Jerome Brunet | 2018-07-09 | 1 | -35/+2 |
* | clk: meson: axg: let mpll clocks round closest | Jerome Brunet | 2018-05-21 | 1 | -0/+4 |
* | clk: meson: Drop unused local variable and add static | Stephen Boyd | 2018-03-14 | 1 | -2/+2 |
* | clk: meson: add fdiv clock gates | Jerome Brunet | 2018-03-13 | 1 | -10/+85 |
* | clk: meson: add mpll pre-divider | Jerome Brunet | 2018-03-13 | 1 | -4/+20 |
* | clk: meson: axg: add hifi pll clock | Jerome Brunet | 2018-03-13 | 1 | -0/+55 |
* | clk: meson: add gp0 frac parameter for axg and gxl | Jerome Brunet | 2018-03-13 | 1 | -1/+6 |
* | clk: meson: remove special gp0 lock loop | Jerome Brunet | 2018-03-13 | 1 | -1/+0 |
* | clk: meson: poke pll CNTL last | Jerome Brunet | 2018-03-13 | 1 | -1/+1 |
* | clk: meson: use hhi syscon if available | Jerome Brunet | 2018-03-13 | 1 | -13/+30 |
* | clk: meson: split divider and gate part of mpll | Jerome Brunet | 2018-03-13 | 1 | -28/+72 |
* | clk: meson: migrate plls clocks to clk_regmap | Jerome Brunet | 2018-03-13 | 1 | -105/+108 |
* | clk: meson: migrate mplls clocks to clk_regmap | Jerome Brunet | 2018-03-13 | 1 | -124/+121 |
* | clk: meson: migrate muxes to clk_regmap | Jerome Brunet | 2018-03-13 | 1 | -35/+25 |
* | clk: meson: migrate dividers to clk_regmap | Jerome Brunet | 2018-03-13 | 1 | -35/+26 |
* | clk: meson: migrate gates to clk_regmap | Jerome Brunet | 2018-03-13 | 1 | -37/+35 |
* | clk: meson: add regmap to the clock controllers | Jerome Brunet | 2018-03-13 | 1 | -1/+14 |
* | clk: meson: remove obsolete comments | Jerome Brunet | 2018-03-13 | 1 | -5/+0 |
* | clk: meson: only one loop index is necessary in probe | Jerome Brunet | 2018-03-13 | 1 | -4/+4 |
* | clk: meson: use devm_of_clk_add_hw_provider | Jerome Brunet | 2018-03-13 | 1 | -2/+2 |
* | clk: meson: use dev pointer where possible | Jerome Brunet | 2018-03-13 | 1 | -4/+4 |
* | clk: meson: add axg misc bit to the mpll driver | Jerome Brunet | 2018-02-12 | 1 | -0/+20 |
* | clk: meson: axg: fix the od shift of the sys_pll | Yixun Lan | 2018-02-12 | 1 | -1/+1 |
* | clk: meson: axg: add the fractional part of the fixed_pll | Jerome Brunet | 2018-02-12 | 1 | -0/+5 |
* | clk: meson: remove useless pll rate params tables | Jerome Brunet | 2018-02-12 | 1 | -94/+0 |
* | clk: meson-axg: fix potential NULL dereference in axg_clkc_probe() | weiyongjun (A) | 2018-01-10 | 1 | -0/+2 |
* | clk: meson-axg: make local symbol axg_gp0_params_table static | weiyongjun (A) | 2017-12-28 | 1 | -1/+1 |
* | clk: meson-axg: fix return value check in axg_clkc_probe() | weiyongjun (A) | 2017-12-28 | 1 | -1/+1 |
* | clk: meson-axg: add clock controller drivers | Qiufang Dai | 2017-12-14 | 1 | -0/+936 |