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path: root/drivers/clk/meson/clk-pll.c (follow)
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* clk: meson: introduce symbol namespace for amlogic clocksJerome Brunet2024-07-291-3/+4
* clk: meson: add 'NOINIT_ENABLED' flag to eliminate init for enabled PLLDmitry Rokosov2024-06-101-16/+24
* clk: meson: fix module license to GPL onlyNeil Armstrong2024-04-101-1/+1
* clk: meson: pll: print out pll name when unable to lock itDmitry Rokosov2024-03-291-2/+2
* clk: meson: change usleep_range() to udelay() for atomic contextDmitry Rokosov2023-07-111-2/+2
* clk: meson: pll: remove unneeded semicolonJiapeng Chong2023-06-151-1/+1
* clk: meson: introduce new pll power-on sequence for A1 SoC familyDmitry Rokosov2023-05-301-0/+23
* clk: meson: make pll rst bit as optionalDmitry Rokosov2023-05-301-7/+17
*-. Merge branches 'clk-bindings', 'clk-renesas', 'clk-amlogic', 'clk-allwinner' ...Stephen Boyd2022-12-121-8/+12
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| | * clk: meson: pll: add pcie lock retry workaroundHeiner Kallweit2022-11-081-4/+8
| | * clk: meson: pll: adjust timeout in meson_clk_pll_wait_lock()Heiner Kallweit2022-11-081-4/+4
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* / clk: Remove a useless includeChristophe JAILLET2022-11-231-1/+0
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* clk: meson: pll: switch to determine_rate for the PLL opsMartin Blumenstingl2021-05-191-11/+15
* clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()Martin Blumenstingl2021-01-041-2/+3
* clk: meson: clk-pll: make "ret" a signed integerMartin Blumenstingl2021-01-041-1/+2
* clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLLMartin Blumenstingl2021-01-041-1/+1
*-. Merge branches 'clk-debugfs-danger', 'clk-basic-hw', 'clk-renesas', 'clk-amlo...Stephen Boyd2020-01-311-0/+9
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| | * clk: meson: pll: Fix by 0 division in __pll_params_to_rate()Remi Pommarel2019-12-161-0/+9
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* / clk: let init callback return an error codeJerome Brunet2019-12-241-1/+3
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*---. Merge branches 'clk-doc', 'clk-more-critical', 'clk-meson' and 'clk-basic-be'...Stephen Boyd2019-05-071-0/+26
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| | * | clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLLNeil Armstrong2019-04-011-0/+26
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* | / clk: meson: pll: fix rounding and setting a rate that matches preciselyMartin Blumenstingl2019-03-251-1/+1
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* | clk: meson: pll: update driver for the g12aJerome Brunet2019-02-041-57/+146
* | clk: meson: rework and clean drivers dependenciesJerome Brunet2019-02-021-4/+9
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* clk: meson: clk-pll: check if the clock is already enabledMartin Blumenstingl2018-11-231-0/+19
* clk: meson: clk-pll: drop hard-coded rates from pll tablesJerome Brunet2018-09-261-23/+46
* clk: meson: clk-pll: remove od parametersJerome Brunet2018-09-261-27/+13
* clk: meson: clk-pll: add enable bitJerome Brunet2018-09-261-5/+42
* clk: meson: use SPDX license identifiers consistentlyJerome Brunet2018-05-181-12/+1
* clk: meson: add ROUND_CLOSEST to the pll driverJerome Brunet2018-03-131-4/+13
* clk: meson: improve pll driver results with fracJerome Brunet2018-03-131-47/+90
* clk: meson: remove special gp0 lock loopJerome Brunet2018-03-131-11/+1
* clk: meson: migrate plls clocks to clk_regmapJerome Brunet2018-03-131-150/+93
* clk: meson: fix rate calculation of plls with a fractional partJerome Brunet2018-02-121-1/+0
* clk: meson: add od3 to the pll driverJerome Brunet2018-02-121-3/+16
* clk: meson: use the frac parameter width instead of a constantJerome Brunet2018-02-121-1/+1
* clk: meson: remove unnecessary rounding in the pll clockJerome Brunet2018-02-121-8/+9
* clk: meson: check pll rate param table before using itJerome Brunet2018-02-121-0/+10
* clk: meson: Add support for parameters for specific PLLsNeil Armstrong2017-04-041-2/+51
* clk: meson: fractional pll supportMichael Turquette2016-06-231-2/+30
* clk: meson8b: clean up pll clocksMichael Turquette2016-06-231-61/+11
* clk: meson: Add support for Meson clock controllerCarlo Caione2015-06-061-0/+227
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