| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r) | Lad Prabhakar | 2020-09-04 | 1 | -1/+1 |
| * | clk: renesas: Convert to SPDX identifiers | Kuninori Morimoto | 2018-09-29 | 1 | -4/+1 |
| * | clk: renesas: r8a7792: Fix LB clock divider | Geert Uytterhoeven | 2018-04-16 | 1 | -1/+1 |
| * | clk: renesas: r8a7792: Add rwdt clock | Geert Uytterhoeven | 2018-02-20 | 1 | -0/+2 |
| * | clk: renesas: r8a7792: Add IMR-LX3/LSX3 clocks | Geert Uytterhoeven | 2017-07-17 | 1 | -0/+7 |
| * | clk: renesas: r8a7792: Add new CPG/MSSR driver | Geert Uytterhoeven | 2017-05-24 | 1 | -0/+221 |
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