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path:
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/
drivers
/
clk
/
renesas
/
r8a77995-cpg-mssr.c
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Commit message (
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Author
Age
Files
Lines
*
clk: renesas: r8a7799[05]: Add MLP clocks
Nikita Yushchenko
2022-01-24
1
-0
/
+1
*
clk: renesas: rcar-gen3: Add SDnH clock
Wolfram Sang
2021-11-19
1
-1
/
+2
*
clk: renesas: r8a77995: Add ZA2 clock
Kuninori Morimoto
2021-05-27
1
-0
/
+1
*
clk: renesas: r8a77995: Add TMU clocks
Niklas Söderlund
2020-12-28
1
-0
/
+5
*
clk: renesas: rcar-gen3: Mark RWDT clocks as critical
Ulrich Hecht
2020-06-22
1
-1
/
+1
*
clk: renesas: rcar-gen3: Add CCREE clocks
Geert Uytterhoeven
2020-02-10
1
-0
/
+2
*
clk: renesas: r8a77995: Add CMM clocks
Jacopo Mondi
2019-06-18
1
-0
/
+2
*
clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC
Takeshi Kihara
2019-04-02
1
-1
/
+1
*
clk: renesas: r8a77995: Simplify PLL3 multiplier/divider
Geert Uytterhoeven
2018-12-04
1
-2
/
+2
*
clk: renesas: r8a77995: Add missing CPEX clock
Geert Uytterhoeven
2018-12-04
1
-1
/
+2
*
clk: renesas: r8a77995: Remove non-existent SSP clocks
Geert Uytterhoeven
2018-12-04
1
-1
/
+0
*
clk: renesas: r8a77995: Remove non-existent VIN5-7 module clocks
Geert Uytterhoeven
2018-12-04
1
-3
/
+0
*
clk: renesas: r8a77995: Correct parent clock of DU
Geert Uytterhoeven
2018-12-04
1
-2
/
+2
*
Merge branch 'clk-renesas' into clk-next
Stephen Boyd
2018-10-19
1
-2
/
+10
|
\
|
*
clk: renesas: r8a77995: Correct RCLK handling
Geert Uytterhoeven
2018-08-27
1
-2
/
+10
*
|
clk: renesas: use SPDX identifier for Renesas drivers
Wolfram Sang
2018-08-31
1
-4
/
+1
|
/
*
clk: renesas: r8a77995: Correct parent clock of INTC-AP
Geert Uytterhoeven
2017-10-16
1
-1
/
+1
*
clk: renesas: cpg-mssr: Add R8A77995 support
Geert Uytterhoeven
2017-08-16
1
-0
/
+236