| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: renesas: rcar-gen3: Switch to new SD clock handling | Wolfram Sang | 2021-11-19 | 1 | -193/+27 |
| * | clk: renesas: rcar-gen3: Add dummy SDnH clock | Wolfram Sang | 2021-11-19 | 1 | -0/+9 |
| * | clk: renesas: cpg-lib: Move RPC clock registration to the library | Wolfram Sang | 2021-10-08 | 1 | -0/+83 |
| * | clk: renesas: Zero init clk_init_data | Geert Uytterhoeven | 2021-03-30 | 1 | -1/+1 |
| * | clk: renesas: rcar-gen3: Factor out CPG library | Wolfram Sang | 2021-01-12 | 1 | -0/+270 |
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