| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC | Biju Das | 2022-02-10 | 1 | -0/+1 |
| * | clk: renesas: r9a07g044: Add mux and divider for G clock | Biju Das | 2021-12-08 | 1 | -0/+4 |
| * | clk: renesas: rzg2l: Add CPG_PL1_DDIV macro | Biju Das | 2021-11-19 | 1 | -0/+2 |
| * | clk: renesas: rzg2l: Add missing kerneldoc for resets | Geert Uytterhoeven | 2021-11-15 | 1 | -0/+3 |
| * | clk: renesas: r9a07g044: Add SDHI clock and reset entries | Biju Das | 2021-10-08 | 1 | -0/+4 |
| * | clk: renesas: rzg2l: Add SDHI clk mux support | Biju Das | 2021-10-08 | 1 | -0/+12 |
| * | clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Co... | Lad Prabhakar | 2021-10-08 | 1 | -0/+3 |
| * | clk: renesas: rzg2l: Add support to handle coupled clocks | Biju Das | 2021-09-24 | 1 | -1/+10 |
| * | clk: renesas: r9a07g044: Add ethernet clock sources | Biju Das | 2021-09-24 | 1 | -0/+3 |
| * | clk: renesas: rzg2l: Add support to handle MUX clocks | Biju Das | 2021-09-24 | 1 | -0/+12 |
| * | clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch] | Geert Uytterhoeven | 2021-07-19 | 1 | -0/+155 |
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