summaryrefslogtreecommitdiffstats
path: root/drivers/clk/rockchip/clk-rk3368.c (follow)
Commit message (Expand)AuthorAgeFilesLines
* clk: rockchip: rk3368: Drop CLK_NR_CLKS usageJohan Jonker2024-08-281-1/+4
* clk: rockchip: support more core div settingElaine Zhang2021-03-211-6/+8
* clk: rockchip: fix DPHY gate locations on rk3368Heiko Stuebner2021-02-061-2/+2
* clk: rockchip: use clock id for SCLK_VIP_OUT on rk3368Heiko Stuebner2021-02-061-1/+1
* clk: rockchip: use clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368Heiko Stuebner2021-02-061-2/+2
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-07-171-9/+3
|\
| * clk: rockchip: convert pclk_wdt boilerplat to new SGRF_GATE macroHeiko Stuebner2019-06-151-9/+3
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner2019-05-301-10/+1
|/
* clk: Remove io.h from clk-provider.hStephen Boyd2019-05-151-0/+1
* clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCsRomain Perier2017-10-141-1/+1
* clk: rockchip: mark some special clk as critical on rk3368Elaine Zhang2017-06-021-1/+4
* clk: rockchip: mark some rk3368 core-clks as criticalElaine Zhang2017-03-101-0/+3
* clk: rockchip: export SCLK_TIMERXX id for timers on rk3368Elaine Zhang2017-03-101-12/+12
* clk: rockchip: release io resource when failing to init clkShawn Lin2016-03-271-0/+1
* clk: rockchip: Add support for multiple clock providersXing Zheng2016-03-271-7/+14
* clk: rockchip: allow varying mux parameters for cpuclk pll-sourcesXing Zheng2016-03-271-0/+6
* Merge tag 'v4.6-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/g...Stephen Boyd2016-03-041-37/+60
|\
| * clk: rockchip: include downstream muxes into fractional dividers on rk3368Elaine Zhang2016-02-261-37/+60
* | Merge tag 'v4.6-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/g...Michael Turquette2016-02-151-49/+33
|\|
| * clk: rockchip: convert manually created factor clocks to the new typeHeiko Stuebner2016-02-041-22/+6
| * clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for i2s_2chzhangqing2016-01-251-1/+1
| * clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for spdif_8chzhangqing2016-01-251-1/+1
| * clk: rockchip: rk3368: fix edp_24m parentzhangqing2016-01-251-1/+1
| * clk: rockchip: rk3368: fix hdmi_cec gate-registerHeiko Stuebner2016-01-241-1/+1
| * clk: rockchip: rk3368: fix parents of video encoder/decoderHeiko Stuebner2016-01-241-2/+2
| * clk: rockchip: rk3368: fix cpuclk core dividersHeiko Stuebner2016-01-241-20/+20
| * clk: rockchip: rk3368: fix cpuclk mux bit of big cpu-clusterHeiko Stuebner2016-01-241-1/+1
* | clk: rockchip: rk3368: fix some clock gatesJianqun xu2016-01-161-13/+13
|/
* clk: rockchip: only enter pll slow-mode directly before reboots on rk3288Heiko Stuebner2015-12-211-1/+1
* clk: rockchip: fix rk3368 cpuclk divider offsetsHeiko Stuebner2015-12-031-2/+2
* clk: rockchip: protect rk3368 aclk_bus and aclk_peri clocksJianqun xu2015-12-021-0/+2
* clk: rockchip: Force rk3368 PWM clock (and its parents) onCaesar Wang2015-12-021-0/+5
* clk: rockchip: add critical clock for rk3368Heiko Stübner2015-09-141-0/+6
* clk: rockchip: add rk3368 clock controllerHeiko Stuebner2015-07-071-0/+881
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-28 12:49:23 +0100