summaryrefslogtreecommitdiffstats
path: root/drivers/clk/rockchip (follow)
Commit message (Expand)AuthorAgeFilesLines
* Merge tag 'v3.19-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/...Michael Turquette2014-11-297-50/+302
|\
| * clk: rockchip: Add support for the mmc clock phases using the frameworkAlexandru M Stan2014-11-285-0/+198
| * clk: rockchip: rk3288 export i2s0_clkout for use in DTSonny Rao2014-11-281-1/+1
| * clk: rockchip: use clock ID for DMC (memory controller) on rk3288Jeff Chen2014-11-261-4/+4
| * clk: rockchip: add ROCKCHIP_PLL_SYNC_RATE flag to some pllsHeiko Stuebner2014-11-252-5/+5
| * clk: rockchip: add optional sync to pll rate parametersHeiko Stuebner2014-11-252-0/+56
| * clk: rockchip: setup pll_mux data earlierHeiko Stuebner2014-11-251-14/+13
| * clk: rockchip: add ability to specify pll-specific flagsHeiko Stuebner2014-11-255-13/+19
| * clk: rockchip: fix rk3188 USB HSIC PHY clock dividerJulien CHAUVEAU2014-11-231-1/+1
| * clk: rockchip: fix clock gate for rk3188 spdif_preJulien CHAUVEAU2014-11-231-16/+9
| * clk: rockchip: fix parent clock for rk3188 hclk_lcdc1Julien CHAUVEAU2014-11-181-1/+1
* | Merge branch 'clk-fixes' into clk-nextMichael Turquette2014-11-251-3/+1
|\ \ | |/ |/|
| * clk-divider: Fix READ_ONLY when divider > 1James Hogan2014-11-171-3/+1
* | clk: rockchip: fix clock select order for rk3288 usbphy480m_srcKever Yang2014-11-161-2/+2
* | clk: rockchip: fix rk3288 clk_usbphy480m_gate bit location in registerKever Yang2014-11-161-1/+1
* | clk: rockchip: ensure HCLK_VIO2_H2P and PCLK_VIO2_H2P stay enabledDmitry Torokhov2014-11-131-2/+2
* | clk: rockchip: rk3288: add suspend and resumeChris Zhong2014-11-101-0/+60
* | clk: rockchip: fix rk3188 hsadc_frac definitionHeiko Stübner2014-11-071-2/+2
* | clk: rockchip: disable unused clocksKever Yang2014-11-043-92/+83
* | clk: rockchip: change PLL setting for better clock jitterKever Yang2014-10-292-1/+10
* | clk: rockchip: add npll to source of sclk_gpuKever Yang2014-10-201-4/+4
* | clk: rockchip: rk3288: removing the CLK_SET_RATE_PARENT from i2s_clkoutJianqun2014-10-201-1/+1
* | clk: rockchip: add 400MHz and 500MHz for rk3288 clock rateKever Yang2014-10-201-0/+2
* | clk: rockchip: Add CLK_SET_RATE_PARENT to aclk_cpu_preDoug Anderson2014-10-201-1/+1
* | clk: rockchip: fix parent for spdif_8ch_frac on rk3288Sonny Rao2014-10-201-1/+1
|/
* clk: rockchip: add restart handlerHeiko Stübner2014-10-014-0/+30
* clk: rockchip: rk3288: i2s_frac adds flag to set parent's rateJianqun2014-10-011-4/+4
* clk: rockchip: switch to using the new cpuclk type for armclkHeiko Stuebner2014-09-272-6/+169
* clk: rockchip: add new clock-type for the cpuclkHeiko Stuebner2014-09-274-0/+388
* clk: rockchip: make tightly bound armclk child-clocks read-onlyHeiko Stuebner2014-09-272-17/+27
* clk: rockchip: reparent aclk_cpu_pre to the gpllHeiko Stuebner2014-09-271-0/+21
* clk: rockchip: fix rk3288 pll status register locationJianqun2014-09-271-2/+2
* clk: rockchip: fix rk3066 pll status register locationHeiko Stuebner2014-09-271-3/+7
* clk: rockchip: change pll rate without a clk-notifierDoug Anderson2014-09-271-50/+13
* Merge branch 'clk-next-rockchip' into clk-nextMike Turquette2014-09-261-36/+56
|\
| * clk: rockchip: add clock node in PD_VIDEOKever Yang2014-09-261-0/+20
| * clk: rockchip: use the clock id for nodes initKever Yang2014-09-261-34/+34
| * clk: rockchip: add missing rk3288 npll rate tableHeiko Stübner2014-09-251-1/+1
| * clk: rockchip: rk3288: fix softreset register countMark yao2014-09-251-1/+1
* | Merge branch 'clk-fixes' into clk-nextMike Turquette2014-09-171-2/+2
|\ \
| * | clk: rockchip: Fix the clocks for i2c1 and i2c2Doug Anderson2014-09-031-2/+2
| |/
* | clk: rockchip: also protect hclk_peri as criticalHeiko Stübner2014-09-102-0/+2
* | clk: rockchip: protect critical clocks from getting disabledHeiko Stübner2014-09-034-0/+28
* | clk: rockchip: make rockchip_clk_register_branch staticHeiko Stübner2014-09-031-1/+1
* | clk: rockchip: implement the fraction divider branch typeHeiko Stübner2014-09-031-2/+56
|/
* clk: rockchip: add clock controller for rk3288Heiko Stübner2014-07-133-0/+727
* clk: rockchip: add clock driver for rk3188 and rk3066 clocksHeiko Stübner2014-07-132-0/+674
* clk: rockchip: add reset controllerHeiko Stübner2014-07-133-0/+133
* clk: rockchip: add clock type for pll clocks and pll used on rk3066Heiko Stübner2014-07-134-0/+541
* clk: rockchip: add basic infrastructure for clock branchesHeiko Stübner2014-07-133-0/+460
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-12 10:02:30 +0100