| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_56.RULE (pa... | Thomas Gleixner | 2022-06-10 | 1 | -4/+1 |
| * | Update Viresh Kumar's email address | Viresh Kumar | 2015-07-18 | 1 | -1/+1 |
| * | CLK: SPEAr: Correct index scanning done for clock synths | Deepak Sikri | 2012-11-21 | 1 | -0/+3 |
| * | Viresh has moved | Viresh Kumar | 2012-06-20 | 1 | -1/+1 |
| * | SPEAr: clk: Add VCO-PLL Synthesizer clock | Viresh Kumar | 2012-05-12 | 1 | -0/+36 |
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