Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_56.RULE (pa... | Thomas Gleixner | 2022-06-10 | 1 | -4/+1 |
* | CLK: SPEAr: make structure field and function argument as const | Bhumika Goyal | 2017-11-02 | 1 | -2/+2 |
* | Update Viresh Kumar's email address | Viresh Kumar | 2015-07-18 | 1 | -1/+1 |
* | Viresh has moved | Viresh Kumar | 2012-06-20 | 1 | -1/+1 |
* | SPEAr: clk: Add General Purpose Timer Synthesizer clock | Viresh Kumar | 2012-05-12 | 1 | -0/+17 |
* | SPEAr: clk: Add Fractional Synthesizer clock | Viresh Kumar | 2012-05-12 | 1 | -0/+16 |
* | SPEAr: clk: Add Auxiliary Synthesizer clock | Viresh Kumar | 2012-05-12 | 1 | -0/+43 |
* | SPEAr: clk: Add VCO-PLL Synthesizer clock | Viresh Kumar | 2012-05-12 | 1 | -0/+58 |