| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: sprd: add RTC gate for SC9860 | Chunyan Zhang | 2018-03-16 | 1 | -0/+76 |
| * | Merge branch 'clk-divider-container' into clk-next | Stephen Boyd | 2018-01-27 | 1 | -1/+2 |
| * | clk: sprd: add clocks support for SC9860 | Chunyan Zhang | 2017-12-22 | 3 | -0/+1987 |
| * | clk: sprd: add adjustable pll support | Chunyan Zhang | 2017-12-22 | 3 | -0/+375 |
| * | clk: sprd: add composite clock support | Chunyan Zhang | 2017-12-22 | 3 | -0/+112 |
| * | clk: sprd: add divider clock support | Chunyan Zhang | 2017-12-22 | 3 | -0/+166 |
| * | clk: sprd: add mux clock support | Chunyan Zhang | 2017-12-22 | 3 | -0/+151 |
| * | clk: sprd: add gate clock support | Chunyan Zhang | 2017-12-22 | 3 | -0/+171 |
| * | clk: sprd: Add common infrastructure | Chunyan Zhang | 2017-12-22 | 4 | -0/+141 |
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