| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: sunxi-ng: h3: Export MBUS clock | Jernej Skrabec | 2019-11-05 | 1 | -4/+0 |
| * | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 | Thomas Gleixner | 2019-05-30 | 1 | -10/+1 |
| * | clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO | Jernej Skrabec | 2018-03-02 | 1 | -1/+3 |
| * | clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM | Chen-Yu Tsai | 2017-05-31 | 1 | -1/+3 |
| * | clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driver | Icenowy Zheng | 2017-03-06 | 1 | -1/+2 |
| * | clk: sunxi-ng: Add H3 clocks | Maxime Ripard | 2016-07-09 | 1 | -0/+62 |
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