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path: root/drivers/clk/sunxi-ng (follow)
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* clk: sunxi-ng: nkm: remove redundant initialization of tmp_parentColin Ian King2023-11-181-3/+2
*-. Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and ...Stephen Boyd2023-08-3010-55/+205
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| | * clk: sunxi-ng: nkm: Prefer current parent rateFrank Oltmanns2023-08-091-1/+2
| | * clk: sunxi-ng: a64: select closest rate for pll-video0Frank Oltmanns2023-08-091-22/+16
| | * clk: sunxi-ng: div: Support finding closest rateFrank Oltmanns2023-08-091-0/+30
| | * clk: sunxi-ng: mux: Support finding closest rateFrank Oltmanns2023-08-092-12/+39
| | * clk: sunxi-ng: nkm: Support finding closest rateFrank Oltmanns2023-08-092-12/+10
| | * clk: sunxi-ng: nm: Support finding closest rateFrank Oltmanns2023-08-092-11/+50
| | * clk: sunxi-ng: Add helper function to find closest rateFrank Oltmanns2023-08-092-0/+17
| | * clk: sunxi-ng: Add feature to find closest rateFrank Oltmanns2023-08-091-0/+1
| | * clk: sunxi-ng: a64: allow pll-mipi to set parent's rateFrank Oltmanns2023-08-091-1/+2
| | * clk: sunxi-ng: nkm: consider alternative parent rates when determining rateFrank Oltmanns2023-08-091-1/+43
| | * clk: sunxi-ng: nkm: Use correct parameter name for parent HWFrank Oltmanns2023-08-091-1/+1
| | * clk: sunxi-ng: Modify mismatched function nameZhang Jianhua2023-07-311-1/+1
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* / clk: Explicitly include correct DT includesRob Herring2023-07-197-6/+8
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* clk: sunxi-ng: a64: force select PLL_MIPI in TCON0 muxRoman Beranek2023-05-181-1/+13
* clk: sunxi-ng: d1: Add CAN bus gates and resetsFabien Poussin2023-01-082-1/+12
* clk: sunxi-ng: d1: Mark cpux clock as criticalAndrás Szemző2023-01-081-1/+1
* clk: sunxi-ng: d1: Allow building for R528/T113Samuel Holland2023-01-081-4/+4
* clk: sunxi-ng: Move SoC driver conditions to dependenciesSamuel Holland2023-01-081-22/+24
* clk: sunxi-ng: Remove duplicate ARCH_SUNXI dependenciesSamuel Holland2023-01-081-22/+21
* clk: sunxi-ng: Avoid computing the rate twiceSamuel Holland2023-01-085-23/+26
* clk: sunxi-ng: h3/h5: Model H3 CLK_DRAM as a fixed clockSamuel Holland2023-01-081-5/+10
* clk: sunxi-ng: fix ccu_mmc_timing.c kernel-doc issuesRandy Dunlap2023-01-081-4/+4
* clk: sunxi-ng: f1c100s: Add IR mod clockAndre Przywara2022-11-162-2/+11
* clk: sunxi-ng: v3s: Correct the header guard of ccu-sun8i-v3s.hWei Li2022-11-161-3/+3
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2022-10-084-38/+26
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| * clk: sunxi-ng: ccu-sun9i-a80-usb: Use dev_err_probe() helperYang Yingliang2022-09-081-6/+3
| * clk: sunxi-ng: ccu-sun9i-a80-de: Use dev_err_probe() helperYang Yingliang2022-09-081-13/+6
| * clk: sunxi-ng: sun8i-de2: Use dev_err_probe() helperYang Yingliang2022-09-081-19/+9
| * clk: sunxi-ng: d1: Limit PLL rates to stable rangesSamuel Holland2022-08-251-0/+8
* | clk: sunxi-ng: h6: Fix default PLL GPU rateJernej Skrabec2022-09-291-2/+6
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* clk: sunxi-ng: sun50i: h6: Modify GPU clock configuration to support DFSRoman Stratiienko2022-07-081-3/+13
* clk: sunxi-ng: Deduplicate ccu_clks arraysSamuel Holland2022-06-065-289/+37
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2022-05-284-2/+15
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| * clk: sunxi-ng: h616: Add PLL derived 32KHz clockAndre Przywara2022-05-062-1/+9
| * clk: sunxi-ng: h6-r: Add RTC gate clockAndre Przywara2022-05-062-1/+6
* | Revert "clk: sunxi-ng: sun6i-rtc: Add support for H6"Jernej Skrabec2022-05-171-15/+0
* | clk: sunxi-ng: sun6i-rtc: Mark rtc-32k as criticalSamuel Holland2022-04-241-0/+1
* | clk: sunxi-ng: fix not NULL terminated coccicheck errorWan Jiabing2022-04-061-0/+1
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* clk: sunxi-ng: sun6i-rtc: include clk/sunxi-ng.hAlexandre Belloni2022-03-251-0/+2
* clk: sunxi-ng: sun6i-rtc: Add support for H6Samuel Holland2022-03-231-0/+15
* clk: sunxi-ng: Add support for the sun6i RTC clocksSamuel Holland2022-03-234-0/+400
* clk: sunxi-ng: mux: Allow muxes to have keysSamuel Holland2022-03-232-0/+8
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2022-01-1344-237/+2256
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| * clk: sunxi-ng: Add support for the D1 SoC clocksSamuel Holland2021-11-236-0/+1576
| * clk: sunxi-ng: gate: Add macros for gates with fixed dividersSamuel Holland2021-11-231-1/+31
| * clk: sunxi-ng: mux: Add macros using clk_parent_data and clk_hwSamuel Holland2021-11-231-0/+33
| * clk: sunxi-ng: mp: Add macros using clk_parent_data and clk_hwSamuel Holland2021-11-231-0/+49
| * clk: sunxi-ng: div: Add macros using clk_parent_data and clk_hwSamuel Holland2021-11-231-0/+78
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-04 16:15:27 +0100