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path: root/drivers/clk/tegra/clk-divider.c (follow)
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* clk: tegra: divider: Check UART's divider enable-bit state on rate's recalcul...Dmitry Osipenko2020-01-101-2/+7
* clk: tegra: divider: Save and restore divider rateSowjanya Komatineni2019-11-111-0/+11
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner2019-05-301-12/+1
* clk: tegra: divider: Mark Memory Controller clock as read-onlyDmitry Osipenko2019-04-251-1/+2
*-. Merge branches 'clk-imx6-ocram', 'clk-missing-put', 'clk-tegra-sdmmc-jitter',...Stephen Boyd2018-08-151-25/+5
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| | * clk: tegra: Refactor fractional divider calculationPeter De Schrijver2018-07-251-25/+5
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* / clk: tegra: Mark Memory Controller clock as criticalDmitry Osipenko2018-07-091-2/+3
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* tegra/clk-divider: fix wrong do_div() usageNicolas Pitre2015-11-161-2/+2
* clk: tegra: Properly include clk.hStephen Boyd2015-07-201-1/+0
* clk: tegra: Implement memory-controller clockThierry Reding2014-11-261-0/+13
* clk: tegra: use max divider if divider overflowsAndrew Bresticker2014-02-171-1/+1
* clk: tegra: add Tegra specific clocksPrashant Gaikwad2013-01-281-0/+187