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path: root/drivers/clk/tegra/clk-pll.c (follow)
Commit message (Expand)AuthorAgeFilesLines
* clk: tegra: Support runtime PM and power domainDmitry Osipenko2021-12-151-1/+1
* clk: tegra: Don't allow zero clock rate for PLLsDmitry Osipenko2021-05-311-0/+3
* clk: tegra: Ensure that PLLU configuration is applied properlyDmitry Osipenko2021-05-311-5/+4
* clk: tegra: Don't enable PLLE HW sequencer at initJC Kuo2021-03-241-12/+0
* clk: tegra: Always program PLL_E when enabledThierry Reding2020-09-211-3/+0
* clk: tegra: Capitalization fixesThierry Reding2020-09-211-2/+2
* clk: tegra: pll: Improve PLLM enable-state detectionDmitry Osipenko2020-07-281-5/+15
* clk: tegra: pll: Add pre/post rate-change hooksDmitry Osipenko2020-05-121-1/+11
* clk: tegra: pll: Save and restore pll contextSowjanya Komatineni2019-11-111-32/+54
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner2019-05-301-12/+1
* clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides dividerDmitry Osipenko2019-04-251-2/+2
* clk: tegra: Don't enable already enabled PLLsDmitry Osipenko2019-04-201-13/+37
* clk: tegra: Return the exact clock rate from clk_round_rateRobert Yang2018-12-141-3/+4
* clk: tegra: Fix pll_u rate configurationMarcel Ziswiler2018-03-121-0/+2
* clk: tegra: Fix T210 PLLRE registrationAlex Frid2017-08-241-20/+1
* clk: tegra: Update T210 PLLSS (D2/DP) registrationAlex Frid2017-08-241-39/+9
* clk: tegra: Re-factor T210 PLLX registrationAlex Frid2017-08-241-40/+0
* clk: tegra: change post IDDQ release delay to 5usPeter De Schrijver2017-08-241-1/+1
* clk: tegra: Init cfg structure in _get_pll_mnpPeter De Schrijver2017-08-241-0/+2
* clk: tegra: Enable PLL_SS for Tegra210Peter De Schrijver2017-08-241-1/+1
* clk: tegra: fix SS control on PLL enable/disablePeter De Schrijver2017-08-241-20/+24
* clk: tegra: Rework pll_uPeter De Schrijver2017-03-201-174/+0
* clk: tegra: Initialize UTMI PLL when enabling PLLUAndrew Bresticker2016-06-301-0/+505
* clk: tegra: Fix pllre Tegra210 and add pll_re_out1Rhyland Klein2016-04-281-0/+46
* clk: tegra: Fix PLLE SS coefficientsMark Kuo2016-02-021-6/+12
* clk: tegra: Fix typos around clearing PLLE bits during enableRhyland Klein2016-02-021-2/+2
* clk: tegra: Do not disable PLLE when under hardware controlMark Kuo2016-02-021-7/+15
* clk: tegra: pll: Fix potential sleeping-while-atomicAndrew Bresticker2016-02-021-3/+3
* clk: tegra: Read correct IDDQ register in PLL_SS registrationBill Huang2015-12-171-4/+7
* clk: tegra: Fix WARN_ON in PLL_RE registrationBill Huang2015-12-171-1/+2
* clk: tegra: pll: Fix issues with rates for VCO PLLsAndrew Bresticker2015-12-171-4/+12
* clk: tegra: Add support for Tegra210 clocksRhyland Klein2015-12-171-0/+5
* clk: tegra: pll: Add logic for SSBill Huang2015-12-171-1/+24
* clk: tegra: pll: Add dyn_ramp callbackRhyland Klein2015-12-171-0/+7
* clk: tegra: pll: Add Set_default logicBill Huang2015-12-171-11/+28
* clk: tegra: pll: Adjust vco_min if SDM presentBill Huang2015-12-171-0/+28
* clk: tegra: pll: Add support for PLLMB for Tegra210Rhyland Klein2015-12-171-5/+43
* clk: tegra: pll: Add specialized logic for Tegra210Rhyland Klein2015-12-171-2/+322
* clk: tegra: pll: Update PLLM handlingDanny Huang2015-11-201-49/+7
* clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rateRhyland Klein2015-11-201-41/+50
* clk: tegra: pll: Add code to handle if resets are supported by PLLBill Huang2015-11-201-0/+12
* clk: tegra: pll: Add logic for out-of-table rates for T210Rhyland Klein2015-11-201-2/+22
* clk: tegra: pll: Add logic for handling SDM dataRhyland Klein2015-11-201-1/+65
* clk: tegra: pll: Don't unconditionally set LOCK flagsRhyland Klein2015-11-201-9/+2
* clk: tegra: pll: Update warning messageRhyland Klein2015-11-201-1/+2
* clk: tegra: pll: Simplify clk_enable_pathRhyland Klein2015-11-201-54/+22
* clk: tegra: pll: Add tegra_pll_wait_for_lock to clk headerRhyland Klein2015-11-201-0/+5
* clk: tegra: Constify pdiv-to-hw mappingsThierry Reding2015-11-201-3/+3
* clk: tegra: Miscellaneous coding style cleanupsThierry Reding2015-11-181-3/+3
* clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)Stephen Boyd2015-08-251-4/+4
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