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path: root/drivers/clk/tegra/clk-tegra20.c (follow)
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* clk: tegra20: Check whether direct PLLM sourcing is turned off for EMCDmitry Osipenko2018-11-081-0/+10
* clk: tegra20: Turn EMC clock gate into dividerDmitry Osipenko2018-11-081-10/+26
* clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20Dmitry Osipenko2018-05-181-1/+31
* clk: tegra20: Correct parents of CDEV1/2 clocksDmitry Osipenko2018-05-181-4/+2
* clk: tegra20: Add DEV1/DEV2 OSC dividersDmitry Osipenko2018-05-181-0/+14
* clk: tegra: Specify VDE clock rateDmitry Osipenko2018-03-121-0/+1
* clk: tegra20: Correct PLL_C_OUT1 setupDmitry Osipenko2018-03-121-3/+3
* clk: tegra: Mark HCLK, SCLK and EMC as criticalDmitry Osipenko2018-03-121-13/+10
* clk: tegra: Bump SCLK clock rate to 216 MHzDmitry Osipenko2017-11-011-1/+1
* clk: tegra: Use common definition of APBDMA clock gateDmitry Osipenko2017-11-011-5/+1
* clk: tegra: Add AHB DMA clock entryDmitry Osipenko2017-11-011-0/+1
* clk: tegra: Use tegra_clk_register_periph_data()Thierry Reding2017-10-191-3/+1
* treewide: Fix typos in printkMasanari Iida2016-04-281-1/+1
* clk: tegra: Remove CLK_IS_ROOTStephen Boyd2016-03-031-6/+4
* clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rateRhyland Klein2015-11-201-72/+78
* clk: tegra: pll: Don't unconditionally set LOCK flagsRhyland Klein2015-11-201-8/+10
* clk: tegra: Constify pdiv-to-hw mappingsThierry Reding2015-11-201-1/+1
* clk: tegra: Format tables consistentlyThierry Reding2015-11-181-143/+134
* clk: tegra: Miscellaneous coding style cleanupsThierry Reding2015-11-181-3/+2
* clk: tegra: Properly include clk.hStephen Boyd2015-07-201-1/+0
* clk: tegra: Implement memory-controller clockThierry Reding2014-11-261-1/+7
* clk: tegra: Add missing Tegra20 fuse clksPeter De Schrijver2014-02-171-0/+2
* clk: tegra: remove bogus PCIE_XCLKStephen Warren2013-12-121-6/+0
* clk: tegra: implement a reset driverStephen Warren2013-12-121-1/+2
* clk: tegra: add FUSE clock deviceAlexandre Courbot2013-11-261-0/+1
* clk: tegra: move tegra20 to common infraPeter De Schrijver2013-11-261-402/+255
* clk: tegra: move periph clocks to common filePeter De Schrijver2013-11-261-2/+2
* clk: tegra: move fields to tegra_clk_pll_paramsPeter De Schrijver2013-11-261-17/+27
* clk: tegra: common periph_clk_enb_refcnt and clksPeter De Schrijver2013-11-261-27/+9
* clk: tegra: simplify periph clock dataPeter De Schrijver2013-11-261-138/+82
* clk: add CLK_SET_RATE_NO_REPARENT flagJames Hogan2013-08-191-2/+4
* clk: tegra20: Fix incorrect placement of __initdataSachin Kamat2013-08-091-1/+1
* clk: tegra: Use common of_clk_init functionPrashant Gaikwad2013-05-311-1/+2
* clk: tegra: add ac97 controller clockLucas Stach2013-05-211-0/+8
* clk: tegra: remove USB from clk init tableLucas Stach2013-05-211-3/+0
* Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/gi...Linus Torvalds2013-05-041-85/+99
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| * clk: tegra: Add flags to tegra_clk_periph()Peter De Schrijver2013-04-051-1/+1
| * clk: tegra: move from a lock bit idx to a lock maskPeter De Schrijver2013-04-051-10/+10
| * clk: tegra: Add PLL post divider tablePeter De Schrijver2013-04-051-0/+7
| * clk: tegra: Refactor PLL programming codePeter De Schrijver2013-04-051-72/+72
| * clk: tegra: defer application of init tableStephen Warren2013-04-051-1/+6
| * clk: tegra: Fix cdev1 and cdev2 IDsPrashant Gaikwad2013-04-051-1/+1
| * clk: tegra: Make gr2d and gr3d clocks children of pll_cThierry Reding2013-04-051-0/+2
| * Merge branch 'for-3.10/soc' into for-3.10/clkStephen Warren2013-04-051-34/+2
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* | \ Merge tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds2013-05-021-34/+2
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| * \ \ Merge tag 'tegra-for-3.10-fixes' of git://git.kernel.org/pub/scm/linux/kernel...Arnd Bergmann2013-04-091-34/+2
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| | * clk: tegra: No 7.1 super clk dividers on Tegra20Peter De Schrijver2013-03-111-34/+2
* | | clk: tegra: Allow PLLE training to succeedThierry Reding2013-04-011-1/+1
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* / clk: Tegra: Remove duplicate smp_twd clockPrashant Gaikwad2013-03-051-1/+0
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* clk: tegra: initialise parent of uart clocksLaxman Dewangan2013-02-131-2/+5
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