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path: root/drivers/clk/tegra/clk-tegra210.c (follow)
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* Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds2019-06-281-0/+2
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| * clk: tegra210: Fix default rates for HDA clocksJon Hunter2019-06-141-0/+2
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner2019-05-301-12/+1
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* clk: core: replace clk_{readl,writel} with {readl,writel}Jonas Gorski2019-04-231-3/+3
* clk: tegra: Fix maximum audio sync clock for Tegra124/210Jon Hunter2018-12-141-1/+8
* clk: tegra210: Include size.h for compilation easeStephen Boyd2018-10-171-0/+1
* clk: tegra: Fixes for MBIST work aroundJoseph Lo2018-10-171-3/+3
* clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocksPeter De-Schrijver2018-07-251-2/+12
* clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20Dmitry Osipenko2018-05-181-1/+1
* clk: tegra: Mark HCLK, SCLK and EMC as criticalDmitry Osipenko2018-03-121-2/+1
* clk: tegra: MBIST work around for Tegra210Peter De Schrijver2018-03-081-2/+342
* clk: tegra: Add la clock for Tegra210Peter De Schrijver2018-03-081-0/+14
* clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init()Nicolin Chen2017-11-011-2/+2
* clk: tegra: Fix sor1_out clock implementationThierry Reding2017-10-191-0/+47
* clk: tegra: Fix Tegra210 PLLU initializationAlex Frid2017-08-241-2/+4
* clk: tegra: Correct Tegra210 UTMIPLL poweron delayAlex Frid2017-08-241-3/+3
* clk: tegra: Re-factor T210 PLLX registrationAlex Frid2017-08-241-1/+1
* clk: tegra: don't warn for pll_d2 defaults unnecessarilyPeter De Schrijver2017-08-241-2/+4
* clk: tegra: Fix T210 effective NDIV calculationAlex Frid2017-08-241-4/+5
* clk: tegra210: remove non-existing VFIR clockPeter De Schrijver2017-08-241-1/+0
* clk: tegra: disable SSC for PLL_D2Peter De Schrijver2017-08-241-1/+1
* clk: tegra: Don't reset PLL-CX if it is already enabledJon Hunter2017-04-041-4/+4
* clk: tegra: Add missing Tegra210 clocksPeter De Schrijver2017-04-041-0/+7
* clk: tegra: Mark TEGRA210_CLK_DBGAPB as always onPeter De Schrijver2017-03-201-0/+2
* clk: tegra: Add SATA seq input controlPeter De Schrijver2017-03-201-0/+25
* clk: tegra: Add Tegra210 special resetsPeter De Schrijver2017-03-201-0/+85
* clk: tegra: Rework pll_uPeter De Schrijver2017-03-201-23/+272
* clk: tegra: Handle UTMIPLL IDDQPeter De Schrijver2017-03-201-0/+26
* clk: tegra: Add aclkPeter De Schrijver2017-03-201-0/+10
* clk: tegra: Define Tegra210 DMIC clocksPeter De Schrijver2017-03-201-0/+3
* clk: tegra: Define Tegra210 DMIC sync clocksPeter De Schrijver2017-03-201-0/+6
* clk: tegra: Add CEC clockPeter De Schrijver2017-03-201-0/+1
* clk: tegra: Correct tegra210_pll_fixed_mdiv_cfg rate calculationPeter De Schrijver2017-03-201-1/+7
* clk: tegra: Don't warn for PLL defaults unnecessarilyPeter De Schrijver2017-03-201-6/+12
* clk: tegra: Remove non-existing pll_m_out1 clockPeter De Schrijver2017-03-201-5/+0
* clk: tegra: Fix ISP clock modellingPeter De Schrijver2017-03-201-0/+1
* clk: tegra: Fix pll_a1 iddq register, add pll_a1Peter De Schrijver2017-03-201-1/+2
* clk: tegra: Initialize UTMI PLL when enabling PLLUAndrew Bresticker2016-06-301-179/+3
* clk: tegra: Micro-optimize Tegra210 clock setupThierry Reding2016-06-231-4/+4
* clk: tegra: Make sor_safe the parent of dpaux and dpaux1Thierry Reding2016-06-231-2/+2
* clk: tegra: Enable sor1 and sor1_src on Tegra210Thierry Reding2016-06-171-0/+2
* clk: tegra: Disable spread spectrum on pll_d2Thierry Reding2016-06-171-2/+3
* clk: tegra: Fixup post dividers on Tegra210Thierry Reding2016-06-101-47/+47
* remove lots of IS_ERR_VALUE abusesArnd Bergmann2016-05-281-1/+1
* clk: tegra: Fix pllre Tegra210 and add pll_re_out1Rhyland Klein2016-04-281-2/+14
* clk: tegra: Add sor_safe clockThierry Reding2016-04-281-0/+4
* clk: tegra: dpaux and dpaux1 are fixed factor clocksThierry Reding2016-04-281-0/+8
* clk: tegra: Add dpaux1 clockThierry Reding2016-04-281-0/+1
* clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLsAndrew Bresticker2016-04-281-0/+58
* clk: tegra: Fix sparse warnings for functions not declared as staticJon Hunter2016-02-021-17/+19