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path: root/drivers/clk/tegra/clk-tegra30.c (follow)
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* clk: tegra: Remove audio clocks configuration from clock driverSowjanya Komatineni2020-03-121-3/+2
* clk: tegra: Remove tegra_pmc_clk_init along with clk idsSowjanya Komatineni2020-03-121-15/+3
* clk: tegra: Remove CLK_M_DIV fixed clocksSowjanya Komatineni2020-03-121-4/+0
* clk: tegra: Add Tegra OSC to clock lookupSowjanya Komatineni2020-03-121-0/+2
* clk: tegra: Add support for OSC_DIV fixed clocksSowjanya Komatineni2020-03-121-0/+4
* clk: tegra20/30: Explicitly set parent clock for Video DecoderDmitry Osipenko2020-01-101-1/+1
* clk: tegra20/30: Don't pre-initialize displays parent clockDmitry Osipenko2020-01-101-2/+0
* clk: tegra: Optimize PLLX restore on Tegra20/30Dmitry Osipenko2019-11-111-9/+16
* clk: tegra: Add Tegra20/30 EMC clock implementationDmitry Osipenko2019-11-111-11/+27
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner2019-05-301-12/+1
* clk: tegra30: Use Tegra CPU powergate helper functionJon Hunter2018-12-141-3/+3
* clk: tegra: Fix maximum audio sync clock for Tegra124/210Jon Hunter2018-12-141-1/+8
* clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20Dmitry Osipenko2018-05-181-1/+1
* clk: tegra: Specify VDE clock rateDmitry Osipenko2018-03-121-0/+1
* clk: tegra: Mark HCLK, SCLK and EMC as criticalDmitry Osipenko2018-03-121-10/+4
* clk: tegra: Fix cclk_lp divisor registerMichał Mirosław2017-11-011-1/+1
* clk: tegra: Add AHB DMA clock entryDmitry Osipenko2017-11-011-0/+1
* clk: tegra: Make tegra_clk_pll_params __ro_after_initBhumika Goyal2017-10-191-8/+8
* clk: tegra: Use tegra_clk_register_periph_data()Thierry Reding2017-10-191-3/+1
* clk: tegra: Add CEC clockPeter De Schrijver2017-03-201-0/+1
* clk: tegra: Initialize UTMI PLL when enabling PLLUAndrew Bresticker2016-06-301-111/+2
* clk: tegra: Fix PLL_U post divider and initial rate on Tegra30Lucas Stach2016-04-281-5/+6
* clk: tegra: Initialize PLL_C to sane rate on Tegra30Lucas Stach2016-04-281-0/+1
* clk: tegra: pll: Update PLLM handlingDanny Huang2015-11-201-1/+1
* clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rateRhyland Klein2015-11-201-110/+117
* clk: tegra: pll: Don't unconditionally set LOCK flagsRhyland Klein2015-11-201-9/+15
* clk: tegra: Constify pdiv-to-hw mappingsThierry Reding2015-11-201-1/+1
* clk: tegra: Format tables consistentlyThierry Reding2015-11-181-189/+189
* clk: tegra: Miscellaneous coding style cleanupsThierry Reding2015-11-181-10/+5
* clk: tegra: Fix 26 MHz oscillator frequencyThierry Reding2015-11-181-1/+1
* clk: tegra: Modify tegra_audio_clk_init to accept more pllsRhyland Klein2015-10-201-1/+7
* clk: tegra: Properly include clk.hStephen Boyd2015-07-201-1/+0
* clk: tegra: Fix hda2codec_2x clock name for Tegra30Marcel Ziswiler2015-05-131-1/+1
* clk: tegra: Model oscillator as clockThierry Reding2015-04-101-1/+2
* clk: tegra: Use consistent indentationThierry Reding2015-04-101-10/+10
* clk: tegra: Implement memory-controller clockThierry Reding2014-11-261-1/+6
* ARM: tegra: Convert PMC to a driverThierry Reding2014-07-171-1/+1
* ARM: tegra: Move includes to include/soc/tegraThierry Reding2014-07-171-1/+4
* clk: tegra: remove bogus PCIE_XCLKStephen Warren2013-12-121-7/+0
* clk: tegra: implement a reset driverStephen Warren2013-12-121-1/+2
* clk: tegra: add FUSE clock deviceAlexandre Courbot2013-11-261-1/+1
* clk: tegra: Properly setup PWM clock on Tegra30Thierry Reding2013-11-261-1/+3
* clk: tegra: Initialize secondary gr3d clock on Tegra30Thierry Reding2013-11-261-0/+1
* clk: tegra: move tegra30 to common infraPeter De Schrijver2013-11-261-895/+403
* clk: tegra: move periph clocks to common filePeter De Schrijver2013-11-261-2/+2
* clk: tegra: move fields to tegra_clk_pll_paramsPeter De Schrijver2013-11-261-27/+35
* clk: tegra: common periph_clk_enb_refcnt and clksPeter De Schrijver2013-11-261-28/+11
* clk: tegra: simplify periph clock dataPeter De Schrijver2013-11-261-201/+116
* clk: tegra: add TEGRA_DIVIDER_ROUND_UP for periph clksPeter De Schrijver2013-11-261-9/+10
* clk: tegra30: Don't wait for PLL_U lock bitTuomas Tynkkynen2013-08-291-1/+1
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-24 16:58:26 +0100