| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk/zynq/clkc: Add CLK_SET_RATE_PARENT flag to ethernet muxes | Soren Brinkmann | 2013-08-13 | 1 | -4/+6 |
| * | clk/zynq/clkc: Add dedicated spinlock for the SWDT | Soren Brinkmann | 2013-08-13 | 1 | -1/+2 |
| * | arm: zynq: Migrate platform to clock controller | Soren Brinkmann | 2013-05-27 | 1 | -0/+3 |
| * | clk: zynq: Add clock controller driver | Soren Brinkmann | 2013-05-27 | 1 | -0/+533 |
| * | clk: zynq: Factor out PLL driver | Soren Brinkmann | 2013-05-21 | 1 | -0/+235 |
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