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path: root/drivers/cxl/core/port.c (follow)
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* Merge branch 'for-6.2/cxl-xor' into for-6.2/cxlDan Williams2022-12-051-3/+6
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| * cxl/acpi: Support CXL XOR Interleave Math (CXIMS)Alison Schofield2022-12-041-3/+6
* | Merge branch 'for-6.2/cxl-aer' into for-6.2/cxlDan Williams2022-12-051-1/+1
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| * | cxl/core/regs: Make cxl_map_{component, device}_regs() device genericDan Williams2022-12-031-1/+1
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* | cxl/port: Add RCD endpoint port enumerationDan Williams2022-12-051-0/+7
* | cxl/mem: Move devm_cxl_add_endpoint() from cxl_core to cxl_memDan Williams2022-12-051-39/+0
* | cxl/acpi: Extract component registers of restricted hosts from RCRBRobert Richter2022-12-031-6/+47
* | cxl/acpi: Move rescan to the workqueueDan Williams2022-12-031-2/+17
* | cxl: Unify debug messages when calling devm_cxl_add_dport()Robert Richter2022-11-141-14/+34
* | cxl: Unify debug messages when calling devm_cxl_add_port()Robert Richter2022-11-141-12/+39
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* cxl/region: Fix 'distance' calculation with passthrough portsDan Williams2022-11-051-2/+9
* cxl/region: Delete 'region' attribute from root decodersDan Williams2022-08-021-1/+2
* cxl/region: Introduce cxl_pmem_region objectsDan Williams2022-07-261-0/+2
* cxl/region: Add region driver boiler plateDan Williams2022-07-261-0/+9
* cxl/hdm: Commit decoder state to hardwareDan Williams2022-07-251-0/+1
* cxl/region: Program target listsDan Williams2022-07-251-3/+1
* cxl/region: Attach endpoint decodersDan Williams2022-07-251-7/+3
* cxl/acpi: Add a host-bridge index lookup mechanismDan Williams2022-07-251-0/+16
* cxl/region: Enable the assignment of endpoint decoders to regionsDan Williams2022-07-251-0/+9
* cxl/region: Add region creation supportBen Widawsky2022-07-221-0/+39
* cxl/mem: Enumerate port targets before adding endpointsDan Williams2022-07-221-0/+41
* cxl/hdm: Add sysfs attributes for interleave ways + granularityBen Widawsky2022-07-221-0/+23
* cxl/port: Move dport tracking to an xarrayDan Williams2022-07-221-49/+36
* cxl/port: Move 'cxl_ep' references to an xarray per portDan Williams2022-07-221-31/+29
* cxl/port: Record parent dport when adding portsDan Williams2022-07-221-12/+15
* cxl/port: Record dport in endpoint referencesDan Williams2022-07-221-17/+35
* cxl/hdm: Add support for allocating DPA to an endpoint decoderDan Williams2022-07-221-1/+72
* cxl/hdm: Track next decoder to allocateDan Williams2022-07-221-0/+1
* cxl/hdm: Add 'mode' attribute to decoder objectsDan Williams2022-07-221-0/+20
* cxl/core: Define a 'struct cxl_endpoint_decoder'Dan Williams2022-07-211-10/+21
* cxl/core: Define a 'struct cxl_root_decoder'Dan Williams2022-07-211-7/+27
* cxl/core: Define a 'struct cxl_switch_decoder'Dan Williams2022-07-211-63/+129
* cxl/port: Cache CXL host bridge dataDan Williams2022-07-101-1/+17
* cxl/mem: Add a debugfs version of 'iomem' for DPA, 'dpamem'Dan Williams2022-07-101-0/+1
* cxl/debug: Move debugfs init to cxl_core_init()Dan Williams2022-07-101-2/+11
* cxl/core: Drop is_cxl_decoder()Dan Williams2022-07-101-6/+0
* cxl/core: Drop ->platform_res attribute for root decodersDan Williams2022-07-101-22/+6
* cxl/core: Rename ->decoder_range ->hpa_rangeDan Williams2022-07-101-2/+2
* cxl/port: Keep port->uport valid for the entire life of a portDan Williams2022-07-091-2/+2
* cxl/core: Use is_endpoint_decoderBen Widawsky2022-06-211-1/+1
* cxl: Drop cxl_device_lock()Dan Williams2022-04-281-32/+23
* cxl: Replace lockdep_mutex with local lock classesDan Williams2022-04-281-4/+9
* cxl/core/port: Fix NULL but dereferenced coccicheck errorWan Jiabing2022-03-221-1/+4
* cxl/port: Hold port reference until decoder releaseDan Williams2022-02-181-0/+4
* cxl/port: Fix endpoint refcount leakDan Williams2022-02-181-1/+2
* cxl/core: Fix cxl_device_lock() class detectionDan Williams2022-02-111-1/+1
* cxl/core/port: Fix unregister_port() lock assertionDan Williams2022-02-111-4/+20
* cxl/core/port: Fix / relax decoder target enumerationDan Williams2022-02-091-1/+4
* cxl/core/port: Add endpoint decodersBen Widawsky2022-02-091-7/+56
* cxl/core: Move target_list out of base decoder attributesDan Williams2022-02-091-1/+2
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