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path: root/drivers/cxl/cxl.h (follow)
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* Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams2023-06-261-25/+32
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| * cxl/port: Store the downstream port's Component Register mappings in struct c...Robert Richter2023-06-251-0/+2
| * cxl/port: Store the port's Component Register mappings in struct cxl_portRobert Richter2023-06-251-0/+2
| * cxl/pci: Early setup RCH dport component registers from RCRBRobert Richter2023-06-251-0/+2
| * cxl/port: Remove Component Register base address from struct cxl_dportRobert Richter2023-06-251-2/+0
| * cxl/pci: Refactor component register discovery for reuseTerry Bowman2023-06-251-0/+1
| * cxl/core/regs: Add @dev to cxl_register_mapRobert Richter2023-06-251-4/+6
| * cxl: Rename 'uport' to 'uport_dev'Dan Williams2023-06-251-6/+7
| * cxl: Rename member @dport of struct cxl_dport to @dport_devRobert Richter2023-06-251-2/+2
| * cxl/rch: Prepare for caching the MMIO mapped PCIe AER capabilityDan Williams2023-06-251-2/+7
| * cxl/acpi: Probe RCRB later during RCH downstream port creationRobert Richter2023-06-251-9/+3
* | Merge branch 'for-6.5/cxl-perf' into for-6.5/cxlDan Williams2023-06-261-0/+16
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| * | cxl/pci: Find and register CXL PMU devicesJonathan Cameron2023-05-301-0/+13
| * | cxl: Add functions to get an instance of / count regblocks of a given typeJonathan Cameron2023-05-301-0/+3
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* | Merge branch 'for-6.5/cxl-region-fixes' into for-6.5/cxlDan Williams2023-06-261-7/+9
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| * | cxl/region: Flag partially torn down regions as unusableDan Williams2023-06-251-0/+8
| * | cxl/region: Move cache invalidation before region teardown, and before setupDan Williams2023-06-251-7/+1
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* | Merge branch 'for-6.5/cxl-type-2' into for-6.5/cxlDan Williams2023-06-261-6/+5
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| * | Revert "cxl/port: Enable the HDM decoder capability for switch ports"Dan Williams2023-06-251-1/+0
| * | cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEMDan Williams2023-06-251-1/+1
| * | cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}Dan Williams2023-06-251-2/+2
| * | cxl/regs: Clarify when a 'struct cxl_register_map' is input vs outputDan Williams2023-06-251-2/+2
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* / cxl/mbox: Add background cmd handling machineryDavidlohr Bueso2023-05-231-0/+8
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* cxl/port: Enable the HDM decoder capability for switch portsDan Williams2023-05-181-0/+1
* cxl/port: Fix find_cxl_root() for RCDs and simplify itDan Williams2023-04-051-2/+2
* cxl/hdm: Skip emulation when driver manages mem_enableDan Williams2023-04-051-1/+3
* Merge tag 'cxl-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxlLinus Torvalds2023-02-251-2/+94
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| * Merge branch 'for-6.3/cxl-rr-emu' into cxl/nextDan Williams2023-02-151-2/+18
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| | * cxl/hdm: Create emulated cxl_hdm for devices that do not have HDM decodersDave Jiang2023-02-151-1/+2
| | * cxl/hdm: Emulate HDM decoder from DVSEC range registersDave Jiang2023-02-151-1/+2
| | * cxl/port: Export cxl_dvsec_rr_decode() to cxl_portDave Jiang2023-02-151-0/+14
| * | Merge branch 'for-6.3/cxl' into cxl/nextDan Williams2023-02-151-0/+1
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| | * | cxl: add RAS status unmasking for CXLDave Jiang2023-02-141-0/+1
| * | | Merge branch 'for-6.3/cxl-ram-region' into cxl/nextDan Williams2023-02-111-0/+57
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| | * | | cxl/dax: Create dax devices for CXL RAM regionsDan Williams2023-02-111-0/+12
| | * | | tools/testing/cxl: Define a fixed volatile configuration to parseDan Williams2023-02-111-0/+2
| | * | | cxl/region: Add region autodiscoveryDan Williams2023-02-111-0/+29
| | * | | cxl/region: Add a mode attribute for regionsDan Williams2023-02-111-0/+14
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| * | | cxl/mem: Wire up event interruptsDavidlohr Bueso2023-01-271-0/+4
| * | | cxl/mem: Read, trace, and clear events on driver loadIra Weiny2023-01-261-0/+12
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| * / cxl/pci: Move tracepoint definitions to drivers/cxl/core/Dan Williams2023-01-051-0/+2
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* / driver core: make struct bus_type.uevent() take a const *Greg Kroah-Hartman2023-01-271-2/+2
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* cxl: update names for interleave ways conversion macrosDave Jiang2022-12-061-7/+7
* cxl: update names for interleave granularity conversion macrosDave Jiang2022-12-061-6/+7
* Merge branch 'for-6.2/cxl-xor' into for-6.2/cxlDan Williams2022-12-051-2/+9
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| * cxl/acpi: Support CXL XOR Interleave Math (CXIMS)Alison Schofield2022-12-041-2/+9
* | Merge branch 'for-6.2/cxl-aer' into for-6.2/cxlDan Williams2022-12-051-9/+29
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| * | cxl/pci: Add (hopeful) error handling supportDan Williams2022-12-031-0/+1
| * | cxl/pci: Find and map the RAS Capability StructureDan Williams2022-12-031-0/+19
| * | cxl/pci: Prepare for mapping RAS Capability StructureDan Williams2022-12-031-1/+3
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