linux - linux

	Commit message (Expand)	Author	Age	Files	Lines
*	PCI/CXL: Move CXL Vendor ID to pci_ids.h	Dave Jiang	2024-05-08	1	-1/+0
*	cxl/pci: Get rid of pointer arithmetic reading CDAT table	Robert Richter	2024-03-13	1	-0/+24
*	cxl: Calculate and store PCI link latency for the downstream ports	Dave Jiang	2023-12-22	1	-0/+13
*	cxl/pci: Find and register CXL PMU devices	Jonathan Cameron	2023-05-30	1	-0/+1
*	cxl: Wait Memory_Info_Valid before access memory related info	Dave Jiang	2023-05-19	1	-0/+2
*	cxl/pci: Handle truncated CDAT entries	Lukas Wunner	2023-04-04	1	-0/+14
*	Merge branch 'for-6.3/cxl-rr-emu' into cxl/next	Dan Williams	2023-02-15	1	-1/+2
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\| *	cxl/port: Export cxl_dvsec_rr_decode() to cxl_port	Dave Jiang	2023-02-15	1	-1/+2
* \|	cxl/mem: Wire up event interrupts	Davidlohr Bueso	2023-01-27	1	-0/+6
* \|	cxl/pci: Move tracepoint definitions to drivers/cxl/core/	Dan Williams	2023-01-05	1	-0/+3
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*	cxl/core/regs: Make cxl_map_{component, device}_regs() device generic	Dan Williams	2022-12-03	1	-9/+0
*	cxl/port: Read CDAT table	Ira Weiny	2022-07-20	1	-0/+1
*	cxl/port: Reuse 'struct cxl_hdm' context for hdm init	Dan Williams	2022-05-19	1	-1/+1
*	cxl/pci: Drop @info argument to cxl_hdm_decode_init()	Dan Williams	2022-05-19	1	-3/+1
*	cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init()	Dan Williams	2022-05-19	1	-2/+2
*	cxl/mem: Consolidate CXL DVSEC Range enumeration in the core	Dan Williams	2022-05-19	1	-0/+4
*	cxl/pci: Retrieve CXL DVSEC memory info	Ben Widawsky	2022-02-09	1	-0/+13
*	cxl/core/port: Remove @host argument for dport + decoder enumeration	Dan Williams	2022-02-09	1	-1/+1
*	cxl/port: Add a driver for 'struct cxl_port' objects	Ben Widawsky	2022-02-09	1	-0/+1
*	cxl/core: Generalize dport enumeration in the core	Dan Williams	2022-02-09	1	-0/+1
*	cxl/pci: Rename pci.h to cxlpci.h	Dan Williams	2022-02-09	1	-0/+60