| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | cxl/pci: Rename pci.h to cxlpci.h | Dan Williams | 2022-02-09 | 1 | -59/+0 |
| * | cxl/acpi: Map component registers for Root Ports | Ben Widawsky | 2022-02-09 | 1 | -0/+9 |
| * | cxl/pci: Add new DVSEC definitions | Ben Widawsky | 2022-02-09 | 1 | -0/+15 |
| * | cxl: Flesh out register names | Ben Widawsky | 2022-02-09 | 1 | -9/+10 |
| * | cxl/pci: Convert register block identifiers to an enum | Ben Widawsky | 2021-10-29 | 1 | -6/+8 |
| * | cxl/pci: Simplify register setup | Ben Widawsky | 2021-08-06 | 1 | -0/+1 |
| * | cxl/pci: Rename CXL REGLOC ID | Ben Widawsky | 2021-06-18 | 1 | -1/+1 |
| * | cxl/mem: Find device capabilities | Ben Widawsky | 2021-02-17 | 1 | -0/+14 |
| * | cxl/mem: Introduce a driver for CXL-2.0-Type-3 endpoints | Dan Williams | 2021-02-17 | 1 | -0/+17 |
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