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path: root/drivers/gpu/drm/i915/display/intel_ddi.h (follow)
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* drm/i915: drop intel_display.h include from intel_ddi.hJani Nikula2021-11-191-1/+3
* drm/i915: Move intel_ddi_fdi_post_disable() to fdi codeVille Syrjälä2021-10-191-0/+1
* drm/i915: Pass the lane to intel_ddi_level()Ville Syrjälä2021-10-041-1/+2
* drm/i915: Nuke useless .set_signal_levels() wrappersVille Syrjälä2021-10-041-4/+2
* drm/i915: s/intel/hsw/ for hsw/bdw/skl buf transVille Syrjälä2021-06-231-2/+2
* drm/i915: Extend icl_sanitize_encoder_pll_mapping() to all DDI platformsVille Syrjälä2021-03-081-1/+1
* drm/i915: Add encoder->is_clock_enabled()Ville Syrjälä2021-03-081-0/+1
* drm/i915: Move DDI clock readout to encoder->get_config()Ville Syrjälä2021-03-081-2/+6
* drm/i915: Extract hsw_ddi_{enable,disable}_clock()Ville Syrjälä2021-02-161-0/+3
* drm/i915: Introduce .{enable,disable}_clock() encoder vfuncsVille Syrjälä2021-02-161-2/+2
* drm/i915: Use intel_ddi_clk_select() for FDIVille Syrjälä2021-02-161-1/+2
* drm/i915: migrate hsw fdi code to new file.Dave Airlie2021-02-051-2/+6
* drm/i915/hdcp: HDCP stream encryption supportAnshuman Gupta2021-01-131-3/+3
* drm/i915: Eliminate intel_dp.regs.dp_tp_{ctl,status}Ville Syrjälä2020-10-011-0/+5
* drm/i915: Plumb crtc_state to link trainingVille Syrjälä2020-10-011-2/+4
* drm/i915: Use the cpu_transcoder in intel_hdcp to toggle HDCP signallingSean Paul2020-09-011-0/+2
* drm/i915: Add {preemph,voltage}_max() vfuncsVille Syrjälä2020-06-031-3/+0
* drm/i915: Pass encoder all the way to intel_ddi_transcoder_func_reg_val_get()Ville Syrjälä2020-04-201-1/+2
* drm/i915: Pass encoder to intel_ddi_enable_pipe_clock()Ville Syrjälä2020-04-201-1/+2
* drm/i915: Pass atomic state to encoder hooksVille Syrjälä2020-04-031-1/+2
* drm/i915: Move DPLL frequency calculation to intel_dpll_mgr.cImre Deak2020-03-021-2/+0
* drm/i915: significantly reduce the use of <drm/i915_drm.h>Jani Nikula2020-02-271-2/+0
* drm/i915: Call hsw_fdi_link_train() directly()Ville Syrjälä2019-12-181-1/+1
* drm/i915/dp: Add support of BT.2020 Colorimetry to DP MSAGwan-gyeong Mun2019-10-151-1/+2
* drm/i915: move modesetting output/encoder code under display/Jani Nikula2019-06-171-0/+52