summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/display/intel_dpll.c (follow)
Commit message (Expand)AuthorAgeFilesLines
* drm/i915/crtc: rename intel_get_crtc_for_pipe() to intel_crtc_for_pipe()Jani Nikula2021-12-021-1/+1
* drm/i915: split out vlv sideband to a separate fileJani Nikula2021-10-141-1/+1
* drm/i915/dpll: move dpll modeset asserts to intel_dpll.cJani Nikula2021-10-011-0/+22
* drm/i915/pps: move pps (panel) modeset asserts to intel_pps.cJani Nikula2021-10-011-5/+8
* drm/i915: constify the dpll clock vtableDave Airlie2021-09-291-8/+40
* drm/i915: split the dpll clock compute out from display vtable.Dave Airlie2021-09-291-8/+8
* drm/i915: s/pipe/transcoder/ when dealing with PIPECONF/TRANSCONFVille Syrjälä2021-09-151-6/+6
* drm/i915: Flatten hsw_crtc_compute_clock()Ville Syrjälä2021-09-151-9/+11
* drm/i915: Fold i9xx_set_pll_dividers() into i9xx_enable_pll()Ville Syrjälä2021-08-251-0/+3
* drm/i915: Reuse ilk_needs_fb_cb_tune() for the reduced clock as wellVille Syrjälä2021-08-251-2/+2
* drm/i915: Call {vlv,chv}_prepare_pll() from {vlv,chv}_enable_pll()Ville Syrjälä2021-08-251-126/+119
* drm/i915: Program DPLL P1 dividers consistentlyVille Syrjälä2021-08-251-39/+41
* drm/i915: Remove the 'reg' local variableVille Syrjälä2021-08-251-9/+9
* drm/i915: Clean up variable names in old dpll functionsVille Syrjälä2021-08-251-75/+76
* drm/i915: Clean dpll calling conventionVille Syrjälä2021-08-251-74/+68
* drm/i915: Constify struct dpll all overVille Syrjälä2021-08-251-23/+35
* drm/i915: Extract ilk_update_pll_dividers()Ville Syrjälä2021-08-251-8/+17
* drm/i915: Set output_types to EDP for vlv/chv DPLL forcingVille Syrjälä2021-08-251-0/+1
* drm/i915/dg2: Add MPLLB programming for SNPS PHYMatt Roper2021-07-291-5/+7
* drm/i915: Don't include intel_de.h from intel_display_types.hVille Syrjälä2021-05-051-0/+1
* drm/i915/display: rename display version macrosLucas De Marchi2021-04-141-1/+1
* drm/i915/display: Eliminate IS_GEN9_{BC,LP}Matt Roper2021-04-141-4/+2
* drm/i915/display: Eliminate most usage of INTEL_GEN()Matt Roper2021-03-241-6/+6
* drm/i915: migrate pll enable/disable code to intel_dpll.[ch]Dave Airlie2021-02-081-0/+509
* drm/i915: refactor pll code out into intel_dpll.cDave Airlie2021-01-151-0/+1363