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path: root/drivers/gpu/drm/i915/display/intel_dpll_mgr.c (follow)
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* drm/i915: Perform automated conversions for crtc uapi/hw split, base -> uapi.Maarten Lankhorst2019-11-011-10/+10
* drm/i915: Fix PCH reference clock for FDI on HSW/BDWVille Syrjälä2019-10-251-0/+15
* drm/i915: Select DPLL's via maskMatt Roper2019-10-091-22/+26
* drm/i915/tgl: Add the Thunderbolt PLL divider valuesImre Deak2019-10-041-2/+40
* drm/i915/tgl: Fix dkl link trainingJosé Roberto de Souza2019-09-271-7/+7
* drm/i915/tgl: Add dkl phy pll calculationsJosé Roberto de Souza2019-09-251-7/+38
* drm/i915/tgl: re-indent code to prepare for DKL changesLucas De Marchi2019-09-251-53/+66
* drm/i915/tgl: Add support for dkl pll writeVandita Kulkarni2019-09-251-1/+64
* drm/i915/tgl: Add initial dkl pll supportLucas De Marchi2019-09-251-2/+94
* drm/i915/tgl/pll: Set update_active_dpllClinton A Taylor2019-09-231-0/+1
* drm/i915: Prefer encoder->name over port_name()Ville Syrjälä2019-09-021-2/+2
* drm/i915: Wrappers for display register waitsDaniele Ceraolo Spurio2019-08-161-33/+11
* drm/i915: rename intel_drv.h to display/intel_display_types.hJani Nikula2019-08-071-1/+1
* drm/i915/ehl: Use an id of 4 while accessing DPLL4's CR0 and CR1Vivek Kasireddy2019-07-181-4/+14
* drm/i915/tgl: Update DPLL clock reference registerJosé Roberto de Souza2019-07-121-2/+6
* drm/i915/tgl: Add DPLL registersLucas De Marchi2019-07-121-5/+19
* drm/i915/tgl: Add pll managerVandita Kulkarni2019-07-121-1/+18
* drm/i915: Polish intel_shared_dpll_swap_state()Ville Syrjälä2019-07-111-12/+7
* drm/i915: Transition port type checks to phy checksMatt Roper2019-07-111-5/+6
* drm/i915/icl: Clear the shared port PLLs from the new crtc stateImre Deak2019-07-091-5/+7
* drm/i915: Clear the shared PLL from the put_dplls() hookImre Deak2019-07-091-6/+14
* drm/i915/ehl: Add support for DPLL4 (v10)Vivek Kasireddy2019-07-051-4/+43
* drm/i915/display: Handle lost primary_port across suspendChris Wilson2019-07-031-9/+4
* drm/i915: Keep the TypeC port mode fixed when the port is activeImre Deak2019-07-011-1/+27
* drm/i915/icl: Reserve all required PLLs for TypeC portsImre Deak2019-07-011-41/+112
* drm/i915/icl: Split getting the DPLLs to port type specific functionsImre Deak2019-07-011-34/+66
* drm/i915: Sanitize the shared DPLL find/reference interfaceImre Deak2019-07-011-37/+70
* drm/i915: Sanitize the shared DPLL reserve/release interfaceImre Deak2019-07-011-82/+139
* drm/i915: Sanitize the terminology used for TypeC port modesImre Deak2019-07-011-1/+1
* drm/i915: move modesetting core code under display/Jani Nikula2019-06-171-0/+3359