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path: root/drivers/gpu/drm/i915/display/intel_dpll_mgr.c (follow)
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* drm/i915/display: Rename POWER_DOMAIN_DPLL_DC_OFF to POWER_DOMAIN_DC_OFFJosé Roberto de Souza2021-10-201-3/+3
* drm/i915: Move PCH refclock stuff into its own fileVille Syrjälä2021-10-191-0/+1
* drm/i915/tc: Add/use helpers to retrieve TypeC port propertiesImre Deak2021-09-291-2/+3
* drm/i915: Nuke intel_prepare_shared_dpll()Ville Syrjälä2021-08-251-28/+0
* drm/i915: Fold ibx_pch_dpll_prepare() into ibx_pch_dpll_enable()Ville Syrjälä2021-08-251-10/+3
* Merge tag 'drm-intel-next-2021-08-10-1' of git://anongit.freedesktop.org/drm/...Dave Airlie2021-08-121-494/+131
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| * drm/i915: Apply CMTG clock disabling WA while DPLL0 is enabledImre Deak2021-08-031-1/+33
| * drm/i915/display: remove explicit CNL handling from intel_dpll_mgr.cLucas De Marchi2021-07-301-492/+94
| * drm/i915/dg2: Skip shared DPLL handlingMatt Roper2021-07-221-1/+4
* | Merge branch 'topic/revid_steppings' into drm-intel-gt-nextMatt Roper2021-07-151-1/+1
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| * drm/i915/jsl_ehl: Use revid->stepping tablesMatt Roper2021-07-151-1/+1
* | drm/i915/adl_p: Add initial ADL_P WorkaroundsClint Taylor2021-06-151-2/+2
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* drm/i915/adl_p: Add PLL SupportAnusha Srivatsa2021-05-201-17/+52
* drm/i915: Don't include intel_de.h from intel_display_types.hVille Syrjälä2021-05-051-0/+1
* drm/i915/display: move crtc and dpll declarations where they belongJani Nikula2021-04-281-0/+1
* drm/i915/display: rename display version macrosLucas De Marchi2021-04-141-1/+1
* drm/i915/display: Eliminate IS_GEN9_{BC,LP}Matt Roper2021-04-141-3/+3
* drm/i915/display: Eliminate most usage of INTEL_GEN()Matt Roper2021-03-241-10/+10
* drm/i915/display: Fix a typoBhaskar Chowdhury2021-03-191-1/+1
* drm/i915: Use pipes instead crtc indices in PLL state trackingVille Syrjälä2021-03-081-23/+25
* drm/i915: Do intel_dpll_readout_hw_state() after encoder readoutVille Syrjälä2021-03-081-3/+6
* drm/i915/adl_s: Configure DPLL for ADL-SAditya Swarup2021-01-261-4/+34
* Merge tag 'drm-intel-next-queued-2020-11-27' of git://anongit.freedesktop.org...Dave Airlie2020-12-031-41/+70
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| * drm/i915: Use actual readout results for .get_freq()Ville Syrjälä2020-11-161-33/+45
| * drm/i915: Introduce intel_dpll_get_hw_state()Ville Syrjälä2020-11-161-3/+17
| * drm/i915/ehl: Implement W/A 22010492432Tejas Upadhyay2020-11-051-5/+8
* | drm: fix some kernel-doc markupsMauro Carvalho Chehab2020-11-161-1/+1
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* drm/i915/dg1: Enable DPLL for DG1Lucas De Marchi2020-10-151-4/+4
* drm/i915/dg1: Add and setup DPLLs for DG1Aditya Swarup2020-10-151-4/+38
* drm/i915/jsl: Split EHL/JSL platform info and PCI idsTejas Upadhyay2020-10-141-8/+8
* drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clockImre Deak2020-10-061-16/+25
* drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programmingImre Deak2020-10-061-0/+13
* drm/i915/pll: Centralize PLL_ENABLE register lookupAnusha Srivatsa2020-09-161-17/+18
* Merge tag 'v5.9-rc4' into drm-nextDave Airlie2020-09-081-4/+4
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| * treewide: Use fallthrough pseudo-keywordGustavo A. R. Silva2020-08-241-4/+4
* | drm/i915/rkl: Handle HTIMatt Roper2020-08-171-0/+11
* | drm/i915/rkl: Add DPLL4 supportMatt Roper2020-08-171-5/+36
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* drm/i915/icl+: Simplify combo/TBT PLL calculation call-chainImre Deak2020-07-011-37/+27
* drm/i915/tgl+: Fix TBT DPLL fractional divider for 38.4MHz ref clockImre Deak2020-07-011-1/+12
* drm/i915/display/dpll_mgr: Prefer drm_WARN_ON over WARN_ONPankaj Bharadiya2020-04-211-4/+4
* drm/i915: Fix documentation for intel_dpll_get_freq()Imre Deak2020-03-091-0/+7
* drm/i915: Unify the DPLL ref clock frequency trackingImre Deak2020-03-021-56/+119
* drm/i915/hsw: Use the read-out WRPLL/SPLL state instead of reading out againImre Deak2020-03-021-5/+2
* drm/i915/skl, cnl: Split out the WRPLL/LCPLL frequency calculationImre Deak2020-03-021-139/+130
* drm/i915/hsw: Split out the WRPLL, LCPLL, SPLL frequency calculationImre Deak2020-03-021-35/+56
* drm/i915/hsw: Split out the SPLL parameter calculationImre Deak2020-03-021-14/+22
* drm/i915/hsw: Rename the get HDMI/DP DPLL funcs to get WRPLL/LCPLLImre Deak2020-03-021-5/+5
* drm/i915/skl: Parametrize the DPLL ref clock instead of open-coding itImre Deak2020-03-021-9/+12
* drm/i915: Move DPLL frequency calculation to intel_dpll_mgr.cImre Deak2020-03-021-0/+418
* drm/i915: Move the DPLL vfunc inits after the func definesImre Deak2020-03-021-60/+60
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