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path: root/drivers/gpu/drm/i915/display/intel_lvds.c (follow)
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* drm/i915: Clean up some DISPLAY_VER checksVille Syrjälä2023-11-291-1/+1
* drm/i915: Skip some timing checks on BXT/GLK DSI transcodersVille Syrjälä2023-11-291-0/+5
* drm/i915/display: Move lvds_channel_mode module parameter under displayJouni Högander2023-10-261-2/+2
* drm/i915/fdi: Improve FDI BW sharing between pipe B and CImre Deak2023-09-281-3/+7
* drm/i915/lvds: Populate connector->ddcVille Syrjälä2023-09-151-12/+11
* drm/i915/lvds: switch to drm_edid_read_switcheroo()Jani Nikula2023-06-021-11/+2
* drm/i915/display: Add new member to configure PCON color conversionAnkit Nautiyal2023-05-051-0/+1
* drm/i915: Namespace pfit registers properlyVille Syrjälä2023-04-201-1/+1
* drm/i915/pps: split out PPS regs to a separate fileJani Nikula2023-03-301-0/+1
* drm/i915: s/PIPECONF/TRANSCONF/Ville Syrjälä2023-02-171-1/+1
* drm/i915/lvds: s/pipe_config/crtc_state/Ville Syrjälä2023-01-311-23/+23
* drm/i915/lvds: s/intel_encoder/encoder/ etc.Ville Syrjälä2023-01-311-70/+64
* drm/i915/lvds: s/dev_priv/i915/Ville Syrjälä2023-01-311-57/+54
* drm/i915/lvds: Fix whitespaceVille Syrjälä2023-01-311-14/+14
* drm/i915/lvds: Extract intel_lvds_regs.hVille Syrjälä2023-01-311-0/+1
* drm/i915/lvds: Use REG_BIT() & co.Ville Syrjälä2023-01-311-2/+2
* drm/i915/lvds: Use intel_de_rmw()Ville Syrjälä2023-01-311-8/+4
* drm/i915/lvds: Split long linesVille Syrjälä2023-01-311-3/+7
* drm/i915/panel: move panel fixed EDID to struct intel_panelJani Nikula2023-01-261-6/+5
* drm/i915/bios: convert intel_bios_init_panel() to drm_edidJani Nikula2023-01-261-1/+1
* drm/i915/edid: convert DP, HDMI and LVDS to drm_edidJani Nikula2023-01-261-17/+29
* drm/i915: Do panel VBT init early if the VBT declares an explicit panel typeVille Syrjälä2022-12-091-2/+2
* drm/i915: stop including i915_irq.h from i915_trace.hJani Nikula2022-11-111-0/+1
* drm/i915/display: remove drm_device aliasesAndrzej Hajda2022-10-111-6/+5
* drm/i915: Allow alternate fixed modes always for LVDSVille Syrjälä2022-09-281-2/+1
* drm/i915: Simplify intel_panel_add_edid_alt_fixed_modes()Ville Syrjälä2022-09-281-2/+1
* drm/i915: Clean up connector->*_allowed setupVille Syrjälä2022-09-261-2/+0
* drm/i915: Extract intel_attach_scaling_mode_property()Ville Syrjälä2022-09-261-9/+1
* drm/i915: Extract intel_lvds_add_properties()Ville Syrjälä2022-09-261-7/+14
* drm/i915: Pass intel_encoder to to_lvds_encoder()Ville Syrjälä2022-09-261-9/+9
* drm/i915: move vbt to display.vbtJani Nikula2022-08-311-2/+2
* drm/i915/bios: calculate panel type as per child device index in VBTAnimesh Manna2022-06-201-1/+1
* drm/i915: Accept more fixed modes with VRR panelsVille Syrjälä2022-06-011-1/+2
* drm/i915/bios: Determine panel type via PNPID matchVille Syrjälä2022-05-271-1/+2
* drm/i915/bios: Split VBT data into per-panel vs. global partsVille Syrjälä2022-05-271-2/+4
* drm/i915: Allow static DRRS on LVDSVille Syrjälä2022-03-311-1/+2
* drm/i915: Combine the EDID fixed_mode+downclock_mode lookup into oneVille Syrjälä2022-03-311-1/+1
* drm/i915: Put fixed modes directly onto the panel's fixed_modes listVille Syrjälä2022-03-311-18/+13
* drm/i915: Extract intel_panel_encoder_fixed_mode()Ville Syrjälä2022-03-291-6/+1
* drm/i915: Rename intel_panel_vbt_fixed_mode()Ville Syrjälä2022-03-291-1/+1
* drm/i915: Use intel_panel_preferred_fixed_mode() moreVille Syrjälä2022-03-291-5/+6
* drm/i915: Use DRM_MODE_FMT+DRM_MODE_ARG()Ville Syrjälä2022-03-291-2/+2
* drm/i915: Pass intel_connector to intel_panel_{init,fini}()Ville Syrjälä2022-03-291-1/+1
* drm/i915: Introduce intel_panel_get_modes()Ville Syrjälä2022-03-141-8/+1
* drm/i915: Introduce intel_panel_{fixed,downclock}_mode()Ville Syrjälä2022-03-141-1/+2
* drm/i915/lvds: Pass fixed_mode to compute_is_dual_link_lvds()Ville Syrjälä2022-03-141-3/+4
* drm/i915/dpll: move dpll modeset asserts to intel_dpll.cJani Nikula2021-10-011-0/+1
* drm/i915/fdi: move fdi modeset asserts to intel_fdi.cJani Nikula2021-10-011-0/+1
* drm/i915: Introduce intel_panel_compute_config()Ville Syrjälä2021-09-301-2/+3
* drm/i915: Use intel_panel_mode_valid() for DSI/LVDS/(s)DVOVille Syrjälä2021-09-301-4/+6
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