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path: root/drivers/gpu/drm/i915/display/intel_pch_display.c (follow)
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* drm/i915: Relocate a few more pch transcoder bitsVille Syrjälä2022-03-041-0/+17
* drm/i915: Relocate ibx pch port sanitation codeVille Syrjälä2022-03-041-0/+67
* drm/i915: Move framestart_delay to crtc_stateVille Syrjälä2022-03-041-7/+8
* drm/i915: Program pch transcoder m2/n2Ville Syrjälä2022-02-011-6/+30
* drm/i915: Move PCH transcoder M/N setup into the PCH codeVille Syrjälä2022-02-011-0/+24
* drm/i915: Split intel_cpu_transcoder_get_m_n() into M1/N1 vs. M2/N2 variantsVille Syrjälä2022-02-011-4/+4
* drm/i915: Nuke ilk_get_fdi_m_n_config()Ville Syrjälä2022-02-011-2/+4
* drm/i915: Clean up PCH_TRANSCONF/TRANS_DP_CTL bit definesVille Syrjälä2022-01-261-6/+7
* drm/i915: Clean up PIPECONF bit definesVille Syrjälä2022-01-261-4/+3
* drm/i915: Introduce ilk_pch_pre_enable()Ville Syrjälä2022-01-261-0/+14
* drm/i915: Introduce lpt_pch_disable()Ville Syrjälä2021-10-191-1/+11
* drm/i915: Introduce ilk_pch_disable() and ilk_pch_post_disable()Ville Syrjälä2021-10-191-1/+36
* drm/i915: Move iCLKIP readout to the pch codeVille Syrjälä2021-10-191-0/+2
* drm/i915: Extract ilk_pch_get_config()Ville Syrjälä2021-10-191-0/+68
* drm/i915: Move LPT PCH readout codeVille Syrjälä2021-10-191-0/+18
* drm/i915: Clean up the {ilk,lpt}_pch_enable() calling conventionVille Syrjälä2021-10-191-10/+13
* drm/i915: Move PCH modeset code to its own fileVille Syrjälä2021-10-191-0/+365
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