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path: root/drivers/gpu/drm/i915/display/intel_snps_phy.c (follow)
Commit message (Expand)AuthorAgeFilesLines
* drm/i915/display: Don't use "proxy" headersAndy Shevchenko2023-12-041-1/+1
* drm/i915/display: Clean up zero initializersVille Syrjälä2023-10-161-1/+1
* drm/i915: Simplify snps/c10x DPLL state checker calling convetionVille Syrjälä2023-10-061-2/+3
* drm/i915: Constify the snps/c10x PLL state checkersVille Syrjälä2023-10-061-2/+2
* drm/i915/display: add i915 parameter to I915_STATE_WARN()Jani Nikula2023-05-151-1/+1
* drm/i915: Make intel_{mpllb,c10pll}_state_verify() saferVille Syrjälä2023-04-151-0/+5
* drm/i915/dg2: Add HDMI pixel clock frequencies 267.30 and 319.89 MHzAnkit Nautiyal2023-02-241-0/+62
* drm/i915: move snps_phy_failed_calibration to display sub-struct under snpsJani Nikula2023-01-181-1/+1
* drm/i915/snps: switch to intel_de_* register accessors in display codeJani Nikula2022-12-081-8/+7
* drm/i915: stop including i915_irq.h from i915_trace.hJani Nikula2022-11-111-0/+1
* drm/i915/dg2: Add additional HDMI pixel clock frequenciesTaylor, Clinton A2022-08-241-0/+1116
* drm/i915/mpllb: move mpllb state check to intel_snps_phy.cJani Nikula2022-06-171-0/+43
* drm/i915: Require an exact DP link freq match for the DG2 PLLVille Syrjälä2022-05-311-1/+1
* drm/i915/dg2: Support 4k@30 on HDMIVandita Kulkarni2022-05-251-0/+32
* drm/i915/dg2: Skip output init on PHY calibration failureMatt Roper2022-02-251-2/+6
* drm/i915/dg2: Drop 38.4 MHz MPLLB tablesMatt Roper2022-02-191-207/+1
* drm/i915: Fix for PHY_MISC_TC1 offsetJouni Högander2022-02-191-1/+1
* drm/i915/dg2: Print PHY name properly on calibration errorMatt Roper2022-02-181-1/+1
* drm/i915/snps: convert to drm device based loggingJani Nikula2022-01-241-14/+15
* drm/i915: Move SNPS PHY registers to their own headerMatt Roper2022-01-111-0/+1
* drm/i915/snps: use div32 version of MPLLB word clock for UHBRJani Nikula2021-12-071-0/+2
* drm/i915: Query the vswing levels per-lane for snps phyVille Syrjälä2021-11-031-1/+1
* drm/i915: Remove pointless extra namespace from dkl/snps buf trans structsVille Syrjälä2021-10-141-3/+3
* drm/i915: Pass the lane to intel_ddi_level()Ville Syrjälä2021-10-041-1/+1
* drm/i915: Hoover the level>=n_entries WARN into intel_ddi_level()Ville Syrjälä2021-10-041-2/+0
* drm/i915: Nuke useless .set_signal_levels() wrappersVille Syrjälä2021-10-041-3/+4
* drm/i915: s/ddi_translations/trans/Ville Syrjälä2021-09-301-6/+6
* drm/i915/dg2: UHBR tables added for pll programmingAnimesh Manna2021-08-301-0/+147
* drm/i915/snps: constify struct intel_mpllb_state arrays harderJani Nikula2021-08-261-7/+7
* drm/i915/dg2: use existing mechanisms for SNPS PHY translationsJani Nikula2021-08-131-44/+17
* drm/i915/dg2: Update lane disable power state during PSRGwan-gyeong Mun2021-07-291-0/+14
* drm/i915/dg2: Wait for SNPS PHY calibration during display initMatt Roper2021-07-291-0/+15
* drm/i915/dg2: Add vswing programming for SNPS physMatt Roper2021-07-291-0/+54
* drm/i915/dg2: Add MPLLB programming for HDMIMatt Roper2021-07-291-12/+274
* drm/i915/dg2: Add MPLLB programming for SNPS PHYMatt Roper2021-07-291-0/+517
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