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path: root/drivers/gpu/drm/i915/display (follow)
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* Merge tag 'drm-next-2021-02-26' of git://anongit.freedesktop.org/drm/drmLinus Torvalds2021-02-253-4/+1
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| * drm/i915: Nuke INTEL_OUTPUT_FORMAT_INVALIDVille Syrjälä2021-02-233-4/+1
* | Merge tag 'drm-next-2021-02-19' of git://anongit.freedesktop.org/drm/drmLinus Torvalds2021-02-2160-7087/+10200
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| * drm/i915: Disallow plane x+w>stride on ilk+ with X-tilingVille Syrjälä2021-02-173-6/+39
| * drm/i915: Reject 446-480MHz HDMI clock on GLKVille Syrjälä2021-02-081-1/+5
| * Merge tag 'drm-intel-next-2021-01-29' of git://anongit.freedesktop.org/drm/dr...Dave Airlie2021-02-048-179/+282
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| | * drm/i915/dp: Prevent setting the LTTPR LT mode if no LTTPRs are detectedImre Deak2021-01-291-21/+15
| | * drm/i915: Implement async flips for vlv/chvVille Syrjälä2021-01-292-6/+47
| | * drm/i915: Implement async flip for ilk/snbVille Syrjälä2021-01-292-1/+26
| | * drm/i915: Implement async flip for ivb/hswVille Syrjälä2021-01-292-1/+26
| | * drm/i915: Implement async flips for bdwVille Syrjälä2021-01-292-3/+58
| | * drm/i915: Limit plane stride to below TILEOFF.x limitVille Syrjälä2021-01-293-16/+83
| | * drm/i915/gen11+: Only load DRAM information from pcodeJosé Roberto de Souza2021-01-291-72/+8
| | * drm/i915: Fix the MST PBN divider calculationImre Deak2021-01-281-1/+3
| | * drm/i915/hdcp: Disable the QSES check for HDCP 1.4 over MSTSean Paul2021-01-281-11/+1
| | * drm/i915/display: Prevent double YUV range correction on HDR planesAndres Calderon Jaramillo2021-01-282-55/+12
| | * drm/i915: WARN if plane src coords are too bigVille Syrjälä2021-01-272-0/+11
| * | Merge tag 'drm-intel-next-2021-01-27' of git://anongit.freedesktop.org/drm/dr...Dave Airlie2021-01-2937-5035/+6372
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| | * drm/i915/display/vrr: Skip the VRR HW state readout on DSI transcoderManasi Navare2021-01-271-1/+1
| | * drm/i915: Do a bit more initial readout for dbufVille Syrjälä2021-01-261-4/+0
| | * drm/i915: Encapsulate dbuf state handling harderVille Syrjälä2021-01-262-16/+0
| | * drm/i915: Fix vblank evasion with vrrVille Syrjälä2021-01-261-1/+4
| | * drm/i915: Fix vblank timestamps with VRRVille Syrjälä2021-01-263-5/+20
| | * drm/i915: Add vrr state dumpVille Syrjälä2021-01-261-0/+7
| | * drm/i915/display: Helpers for VRR vblank min and max startVille Syrjälä2021-01-262-0/+38
| | * drm/i915/display: Add HW state readout for VRRManasi Navare2021-01-263-0/+26
| | * drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP SinkManasi Navare2021-01-262-1/+20
| | * drm/i915/display/vrr: Disable VRR in modeset disable pathManasi Navare2021-01-263-0/+16
| | * drm/i915/display/vrr: Send VRR push to flip the frameManasi Navare2021-01-263-0/+18
| | * drm/i915/display/vrr: Configure and enable VRR in modeset enableManasi Navare2021-01-263-0/+28
| | * drm/i915/display: VRR + DRRS cannot be enabled togetherVille Syrjälä2021-01-261-0/+3
| | * drm/i915/display/dp: Do not enable PSR if VRR is enabledManasi Navare2021-01-261-0/+7
| | * drm/i915/display/dp: Compute VRR state in atomic_checkManasi Navare2021-01-265-0/+95
| | * drm/i915: Extract intel_mode_vblank_start()Ville Syrjälä2021-01-261-3/+11
| | * drm/i915: Store framestart_delay in dev_privVille Syrjälä2021-01-261-11/+12
| | * drm/i915/display/dp: Attach and set drm connector VRR propertyAditya Swarup2021-01-262-2/+10
| | * drm/i915/display/vrr: Create VRR file and add VRR capability checkManasi Navare2021-01-262-0/+46
| | * drm/i915/tgl: Add Clear Color support for TGL Render DecompressionRadhakrishna Sripada2021-01-223-5/+107
| | * drm/i915/hdcp: Fix uninitialized symbolAnshuman Gupta2021-01-221-10/+10
| | * drm/i915/hdcp: Fix WARN_ON(data->k > INTEL_NUM_PIPES)Anshuman Gupta2021-01-221-0/+2
| | * drm/i915/dp: Don't use DPCD backlights that need PWM enable/disableLyude Paul2021-01-221-1/+6
| | * drm/i915: Unify the sanity checks for the buf trans tablesVille Syrjälä2021-01-211-13/+10
| | * drm/i915: Fix ICL MG PHY vswing handlingVille Syrjälä2021-01-211-4/+3
| | * drm/i915/dp: split out aux functionality to intel_dp_aux.cJani Nikula2021-01-215-681/+713
| | * drm/i915/dp: abstract struct intel_dp pps members to a sub-structJani Nikula2021-01-214-135/+140
| | * drm/i915/pps: move pps code over from intel_display.c and refactorJani Nikula2021-01-214-38/+41
| | * drm/i915/pps: refactor init abstractionsJani Nikula2021-01-211-25/+12
| | * drm/dp: Revert "drm/dp: Introduce EDID-based quirks"Lyude Paul2021-01-194-11/+4
| | * drm/i915/dp: Allow forcing specific interfaces through enable_dpcd_backlightLyude Paul2021-01-191-3/+42
| | * drm/i915/dp: Enable Intel's HDR backlight interface (only SDR for now)Lyude Paul2021-01-194-31/+269
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