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path: root/drivers/gpu/drm/i915/display (follow)
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* drm/i915: Add missing HDMI audio pixel clocks for gen12Kai Vehmanen2020-03-111-0/+8
* drm/i915/overlay: convert to drm_device based logging.Wambui Karuga2020-03-111-5/+6
* drm/i915/lvds: convert to drm_device based logging macros.Wambui Karuga2020-03-111-18/+25
* drm/i915/lpe_audio: convert to drm_device based logging macros.Wambui Karuga2020-03-111-9/+14
* drm/i915/hotplug: convert to drm_device based logging.Wambui Karuga2020-03-111-16/+24
* drm/i915/gmbus: convert to drm_device based logging,Wambui Karuga2020-03-111-14/+19
* drm/i915/fifo_underrun: convert to drm_device based logging.Wambui Karuga2020-03-111-13/+16
* drm/i915/dsb: convert to drm_device based logging macros.Wambui Karuga2020-03-111-12/+16
* drm/i915/display: Do not write in removed FBC fence registersRadhakrishna Sripada2020-03-101-1/+1
* drm/i915/display: Deactive FBC in fastsets when disabled by parameterJosé Roberto de Souza2020-03-101-22/+25
* drm/i915/mst: Hookup DRM DP MST late_register/early_unregister callbacksLyude Paul2020-03-101-2/+31
* drm/i915: Lock gmbus/aux mutexes while changing cdclkVille Syrjälä2020-03-091-0/+22
* drm/i915: Pass the crtc to the low level read_lut() funcsVille Syrjälä2020-03-091-26/+25
* drm/i915: Fix readout of PIPEGCMAXVille Syrjälä2020-03-091-1/+2
* drm/i915: Refactor LUT read functionsVille Syrjälä2020-03-091-61/+63
* drm/i915: Clean up integer types in color codeVille Syrjälä2020-03-091-24/+19
* drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/Ville Syrjälä2020-03-091-2/+2
* drm/i915: s/blob_data/lut/Ville Syrjälä2020-03-091-33/+33
* drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variantsVille Syrjälä2020-03-091-6/+35
* drm/i915: Clean up i9xx_load_luts_internal()Ville Syrjälä2020-03-091-44/+60
* drm/i915: Polish CHV CGM CSC loadingVille Syrjälä2020-03-091-37/+38
* drm/i915: Fix documentation for intel_dpll_get_freq()Imre Deak2020-03-092-0/+13
* drm/i915/hotplug: Use phy to get the hpd_pin instead of the port (v5)Vivek Kasireddy2020-03-061-22/+9
* drm/i915: properly sanity check batch_start_offsetMatthew Auld2020-03-061-6/+6
* drm/i915/display: Decrease log levelSwati Sharma2020-03-051-2/+3
* drm/i915: Add invert-brightness quirk for Thundersoft TST178 tabletHans de Goede2020-03-041-0/+10
* drm/i915: panel: Use intel_panel_compute_brightness() from pwm_setup_backlight()Hans de Goede2020-03-041-7/+11
* drm/i915/ehl: Check PHY type before reading DPLL frequencyMatt Roper2020-03-041-1/+2
* drm/i915: Force DPCD backlight mode on X1 Extreme 2nd Gen 4K AMOLED panelLyude Paul2020-03-041-4/+20
* drm/dp: Introduce EDID-based quirksLyude Paul2020-03-044-6/+10
* drm/i915/hdcp: Fix config_stream_type() ret valueAnshuman Gupta2020-03-041-1/+5
* drm/i915/hdcp: Mandate (seq_num_V==0) at first RecvId msgAnshuman Gupta2020-03-041-0/+6
* drm/i915: Polish CHV .load_luts() a bitVille Syrjälä2020-03-031-7/+4
* drm/i915/vgpu: improve vgpu abstractionsJani Nikula2020-03-032-0/+2
* drm/i915: Fix kbuild test robot build errorAnshuman Gupta2020-03-031-9/+9
* drm/i915/hdcp: conversion to struct drm_device based logging macros.Ramalingam C2020-03-031-47/+62
* drm/i915: move watermark structs more towards usageJani Nikula2020-03-031-0/+16
* drm/i915/dmc: Use firmware v2.06 for TGLJosé Roberto de Souza2020-03-031-2/+2
* drm/i915: Unify the DPLL ref clock frequency trackingImre Deak2020-03-022-56/+124
* drm/i915/hsw: Use the read-out WRPLL/SPLL state instead of reading out againImre Deak2020-03-021-5/+2
* drm/i915/skl, cnl: Split out the WRPLL/LCPLL frequency calculationImre Deak2020-03-024-145/+140
* drm/i915/hsw: Split out the WRPLL, LCPLL, SPLL frequency calculationImre Deak2020-03-021-35/+56
* drm/i915/hsw: Split out the SPLL parameter calculationImre Deak2020-03-021-14/+22
* drm/i915/hsw: Rename the get HDMI/DP DPLL funcs to get WRPLL/LCPLLImre Deak2020-03-021-5/+5
* drm/i915/skl: Parametrize the DPLL ref clock instead of open-coding itImre Deak2020-03-021-9/+12
* drm/i915: Move DPLL frequency calculation to intel_dpll_mgr.cImre Deak2020-03-025-437/+431
* drm/i915/hsw: Use the DPLL ID when calculating DPLL clockImre Deak2020-03-021-9/+8
* drm/i915: Move the DPLL vfunc inits after the func definesImre Deak2020-03-021-60/+60
* drm/i915: Keep the global DPLL state in a DPLL specific structImre Deak2020-03-025-47/+49
* drm/i915: Move DPLL HW readout/sanitize fns to intel_dpll_mgr.cImre Deak2020-03-023-42/+63
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