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path: root/drivers/gpu/drm/i915/intel_ddi.c (follow)
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* drm/i915/icl: Fix DDI/TC port clk_off bitsMahesh Kumar2018-10-181-3/+18
* drm/i915/icl: create function to identify combophy portMahesh Kumar2018-10-181-7/+8
* drm/i915/psr: Enable AUX-A IO power well on ICL for PSRDhinakaran Pandiyan2018-09-191-1/+1
* drm/i915: Fix ICL+ HDMI clock readoutVille Syrjälä2018-09-041-1/+1
* drm/i915/dp_mst: Fix enabling pipe clock for all streamsImre Deak2018-09-011-8/+9
* drm/i915/icl: Get DDI clock for ICL for MG PLL and TBT PLLManasi Navare2018-08-201-2/+79
* drm/i915: set DP Main Stream Attribute for color range on DDI platformsJani Nikula2018-08-141-0/+4
* drm/i915/icl: toggle PHY clock gating around link trainingPaulo Zanoni2018-07-251-0/+3
* drm/i915/icl: program MG_DP_MODEPaulo Zanoni2018-07-251-0/+2
* drm/i915/icl: Implement voltage swing programming sequence for MG PHY DDIManasi Navare2018-07-251-6/+129
* drm/i915: Nuke dev_priv->irq_port[]Ville Syrjälä2018-07-131-1/+0
* drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.Clint Taylor2018-07-131-2/+11
* drm/i915/ddi: Simplify get_encoder_power_domains()Imre Deak2018-07-061-12/+7
* drm/i915: Mark expected switch fall-throughsGustavo A. R. Silva2018-07-051-0/+1
* drm/i915/ddi: Get AUX power domain for DP main link tooImre Deak2018-06-261-4/+50
* drm/i915/icl: implement DVFS for ICLPaulo Zanoni2018-06-161-0/+2
* drm/i915/icl: start adding the TBT pllPaulo Zanoni2018-06-141-0/+16
* drm/i915/ddi: Set HDMI infoframes with pipe clocks enabledImre Deak2018-06-141-5/+5
* drm/i915/ddi: Push pipe clock enabling to encodersImre Deak2018-06-141-0/+8
* drm/i915/icl: Add DDI HDMI level selection for ICLManasi Navare2018-06-121-1/+8
* drm/i915/icl: Calculate link clock using the new registersArkadiusz Hiler2018-06-021-2/+7
* drm/i915/icl: Get DDI clock for ICL based on PLLs.Manasi Navare2018-06-021-0/+26
* drm/i915/icl: fix icl_unmap/map_plls_to_portsMahesh Kumar2018-06-021-2/+4
* drm/i915: Move intel_ddi_get_crtc_new_encoder() out from ddi codeVille Syrjälä2018-05-231-29/+0
* drm/i915: Use the same vswing->max_preemph mapping on HSW/BDW as on SKL+Ville Syrjälä2018-05-181-0/+20
* drm/i915/icl: add basic support for the ICL clocksPaulo Zanoni2018-05-081-4/+94
* drm/i915/icl: Fix the DP Max Voltage for ICLManasi Navare2018-05-011-1/+7
* drm/i915/icl: Implement voltage swing programming sequence for Combo PHY DDIManasi Navare2018-05-011-3/+188
* drm/i915/dp: Send DPCD ON for MST before phy_upLyude Paul2018-04-081-2/+6
* drm/i915: use id from intel_shared_dpll.infoLucas De Marchi2018-03-271-4/+4
* drm/i915/icl: Add Voltage swing table for MG PHY DDI BufferManasi Navare2018-03-231-0/+20
* drm/i915/icl: Add Combo PHY DDI Buffer translation tables for Icelake.Manasi Navare2018-03-231-0/+99
* drm/i915: Don't spew errors when resetting HDMI scrambling/bit clock ratio failsVille Syrjälä2018-03-231-7/+12
* drm/i915/dp: Write to SET_POWER dpcd to enable MST hub.Dhinakaran Pandiyan2018-03-191-5/+2
* drm/i915/icl: do not save DDI A/E sharing bit for ICLJani Nikula2018-03-091-3/+6
* drm/i915: Track whether the DP link is trained or notVille Syrjälä2018-03-061-0/+2
* drm/i915: Move SST DP link retraining into the ->post_hotplug() hookVille Syrjälä2018-03-061-5/+5
* drm/i915: Reinitialize sink scrambling/TMDS clock ratio on HPDVille Syrjälä2018-03-061-0/+146
* drm/i915/icl: remove port A/E lane sharing limitation.Mahesh Kumar2018-03-051-46/+39
* Merge tag 'drm-intel-next-2018-02-21' of git://anongit.freedesktop.org/drm/dr...Dave Airlie2018-03-011-1/+1
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| * drm/i915: Use INTEL_GEN everywhereTvrtko Ursulin2018-02-091-1/+1
* | Merge tag 'topic/hdcp-2018-02-13' of git://anongit.freedesktop.org/drm/drm-mi...Dave Airlie2018-02-161-0/+36
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| * drm/i915: Implement HDCP for HDMISean Paul2018-01-081-0/+29
| * drm/i915: Add HDCP framework + base implementationSean Paul2018-01-081-0/+7
* | drm/i915/cnl: Enable DDI-F on Cannonlake.Rodrigo Vivi2018-01-301-0/+4
* | drm/i915: Implement display w/a #1143Ville Syrjälä2018-01-241-0/+42
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* drm/i915: Fix indentation for intel_ddi_clk_selectChris Wilson2017-12-191-2/+2
* drm/i915: Protect DDI port to DPLL map from theoretical race.Rodrigo Vivi2017-12-181-0/+4
* drm/i915/cnl: Mask previous DDI - PLL mappingJames Ausmus2017-12-011-0/+1
* drm/i915: Fix has_audio readout for DDI AVille Syrjälä2017-12-011-10/+10
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