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path: root/drivers/gpu/drm/i915/intel_dpio_phy.c (follow)
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* drm/i915/gen9_lp: Increase DDI PHY0 power well enabling timeoutImre Deak2018-04-101-5/+6
* drm: intel_dpio_phy: fix kernel-doc comments at nested structMauro Carvalho Chehab2018-02-191-1/+1
* drm/i915: Nuke intel_digital_port->portVille Syrjälä2017-11-091-7/+5
* drm/i915: Pass crtc state to DPIO PHY functionsVille Syrjälä2017-11-091-44/+43
* drm/i915: Simplify onion for bxt_ddi_phy_init()Chris Wilson2017-11-071-10/+10
* drm/i915: Fix BXT lane latency optimal setting with MSTVille Syrjälä2017-10-271-2/+1
* drm/i915: Fix DDI PHY init if it was already onImre Deak2017-10-031-20/+0
* drm/i915: Only poll DW3_A when init DDI PHY for ports B and C.Rodrigo Vivi2016-12-021-12/+3
* drm/i915/glk: Implement Geminilake DDI init sequenceAnder Conselvan de Oliveira2016-12-021-15/+99
* drm/i915/glk: Reuse broxton code for geminilakeAnder Conselvan de Oliveira2016-12-021-1/+0
* drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init sequenceAnder Conselvan de Oliveira2016-11-021-21/+0
* drm/i915: Address broxton phy registers based on phy and channel numberAnder Conselvan de Oliveira2016-10-281-14/+54
* drm/i915: Add location of the Rcomp resistor to bxt_ddi_phy_infoAnder Conselvan de Oliveira2016-10-281-17/+55
* drm/i915: Create a struct to hold information about the broxton physAnder Conselvan de Oliveira2016-10-281-10/+55
* drm/i915: Move broxton vswing sequence to intel_dpio_phy.cAnder Conselvan de Oliveira2016-10-281-0/+39
* drm/i915: Move DPIO phy documentation section to intel_dpio_phy.cAnder Conselvan de Oliveira2016-10-281-0/+91
* drm/i915: Move broxton phy code to intel_dpio_phy.cAnder Conselvan de Oliveira2016-10-281-0/+327
* drm/i915: Mass convert dev->dev_private to to_i915(dev)Chris Wilson2016-07-041-5/+5
* drm/i915: Move VLV HDMI lane reset work around logic to intel_dpio_phy.cAnder Conselvan de Oliveira2016-04-291-0/+15
* drm/i915: Unduplicate pre encoder enabling phy codeAnder Conselvan de Oliveira2016-04-291-0/+30
* drm/i915: Unduplicate VLV phy pre pll enabling codeAnder Conselvan de Oliveira2016-04-291-0/+28
* drm/i915: Unduplicate VLV signal level codeAnder Conselvan de Oliveira2016-04-291-0/+26
* drm/i915: Unduplicate CHV encoders' post pll disable codeAnder Conselvan de Oliveira2016-04-291-0/+33
* drm/i915: Unduplicate CHV pre-encoder enabling phy logicAnder Conselvan de Oliveira2016-04-291-0/+92
* drm/i915: Unduplicate CHV phy-releated pre pll enabling codeAnder Conselvan de Oliveira2016-04-291-0/+81
* drm/i915: Unduplicate chv_data_lane_soft_reset()Ander Conselvan de Oliveira2016-04-291-0/+43
* drm/i915: Unduplicate CHV signal level codeAnder Conselvan de Oliveira2016-04-291-0/+122
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