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path: root/drivers/gpu/drm/i915/intel_psr.c (follow)
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* drm/i915: disable PSR by default on HSW/BDWPaulo Zanoni2016-12-201-7/+3
* drm/i915: Assorted INTEL_INFO(dev) cleanupsTvrtko Ursulin2016-11-171-2/+2
* drm/i915: More assorted dev_priv cleanupsTvrtko Ursulin2016-11-111-1/+1
* drm/i915: Make IS_CHERRYVIEW only take dev_privTvrtko Ursulin2016-10-141-2/+2
* drm/i915: Make IS_HASWELL only take dev_privTvrtko Ursulin2016-10-141-3/+3
* drm/i915: Make IS_BROADWELL only take dev_privTvrtko Ursulin2016-10-141-2/+2
* drm/i915: Make HAS_DDI and HAS_PCH_LPT_LP only take dev_privTvrtko Ursulin2016-10-141-4/+4
* Revert "drm/i915/psr: Make idle_frames sensible again"Rodrigo Vivi2016-09-131-7/+7
* Merge tag 'drm-intel-next-2016-08-08' of git://anongit.freedesktop.org/drm-in...Dave Airlie2016-08-151-15/+11
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| * drm/i915: Use dev_priv consistently through the intel_frontbuffer interfaceChris Wilson2016-08-041-15/+11
* | drm/i915: Check PSR setup time vs. vblank lengthVille Syrjälä2016-08-021-1/+18
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* drm/i915: Mass convert dev->dev_private to to_i915(dev)Chris Wilson2016-07-041-18/+18
* drm/i915: Convert wait_for(I915_READ(reg)) to intel_wait_for_register()Chris Wilson2016-06-301-4/+10
* drm/i915: Convert wait_for(I915_READ(reg)) to intel_wait_for_register()Chris Wilson2016-06-301-3/+5
* drm/i915: Convert wait_for(I915_READ(reg)) to intel_wait_for_register()Chris Wilson2016-06-301-2/+5
* drm/i915/psr: Use ->get_aux_send_ctl functionsDaniel Vetter2016-05-201-21/+4
* drm/i915/psr: Order DP aux transactions correctlyDaniel Vetter2016-05-201-7/+7
* drm/i915/psr: Make idle_frames sensible againDaniel Vetter2016-05-201-7/+7
* drm/i915/psr: Try to program link training times correctlyDaniel Vetter2016-05-201-8/+47
* drm/i915: Do not use {HAS_*, IS_*, INTEL_INFO}(dev_priv->dev)Joonas Lahtinen2016-04-071-1/+1
* Revert "drm/i915: Enable PSR by default on Valleyview and Cherryview."Ville Syrjälä2016-03-101-2/+1
* drm/i915: Add wait_for_usTvrtko Ursulin2016-03-031-1/+2
* drm/i915: Enable PSR by default on Haswell and Broadwell.Rodrigo Vivi2016-02-171-1/+2
* drm/i915: Enable PSR by default on Valleyview and Cherryview.Rodrigo Vivi2016-02-171-1/+4
* drm/i915: Change i915.enable_psr parameter to use per platform default.Rodrigo Vivi2016-02-171-0/+5
* drm/i915: Instrument PSR parameter for debuging with link standby x link off.Rodrigo Vivi2016-02-011-0/+17
* drm/i915: Add PSR main link standby support backRodrigo Vivi2016-02-011-7/+19
* drm/i915: PSR simplify port and link standby checks.Rodrigo Vivi2016-02-011-3/+10
* drm/i915: PSR also doesn't have link_entry_time on SKL.Rodrigo Vivi2015-12-121-2/+3
* drm/i915: Separate cherryview from valleyviewWayne Boyer2015-12-101-3/+3
* drm/i915: Fix idle_frames counter.Rodrigo Vivi2015-12-071-13/+7
* drm/i915: Also disable PSR on Sink when disabling it on Source.Rodrigo Vivi2015-11-241-0/+4
* drm/i915: PSR: Mask LPSP hw tracking back again.Rodrigo Vivi2015-11-241-2/+7
* drm/i915: PSR: Let's rely more on frontbuffer tracking.Rodrigo Vivi2015-11-241-19/+3
* drm/i915: Remove duplicated dpcd write on hsw_psr_enable_sink.Rodrigo Vivi2015-11-241-3/+0
* drm/i915: Send TP1 TP2/3 even when panel claims no NO_TRAIN_ON_EXIT.Rodrigo Vivi2015-11-181-4/+0
* drm/i915: PSR: Don't Skip aux handshake on DP_PSR_NO_TRAIN_ON_EXIT.Rodrigo Vivi2015-11-181-1/+0
* drm/i915: Reduce PSR re-activation time for VLV/CHV.Rodrigo Vivi2015-11-181-2/+1
* drm/i915: Delay first PSR activation.Rodrigo Vivi2015-11-181-2/+16
* drm/i915: Type safe register read/writeVille Syrjälä2015-11-181-6/+6
* drm/i915: Model PSR AUX register selection more like the normal AUX codeVille Syrjälä2015-11-161-6/+21
* drm/i915: Add dev_priv->psr_mmio_baseVille Syrjälä2015-11-161-12/+15
* drm/i915: Parametrize AUX registersVille Syrjälä2015-11-161-2/+3
* drm/i915: Parametrize HSW video DIP data registersVille Syrjälä2015-10-131-8/+10
* drm/i915: VLV/CHV PSR: Increase wait delay time before active PSR.Rodrigo Vivi2015-08-051-1/+2
* drm/i915: PSR: Increase idle_framesRodrigo Vivi2015-07-091-2/+5
* drm/i915: PSR: Remove Low Power HW tracking mask.Rodrigo Vivi2015-07-091-1/+1
* drm/i915: PSR: Flush means invalidate + flushRodrigo Vivi2015-07-091-19/+21
* drm/i915/psr: Restrict single-shot updates to the PSR pipeDaniel Vetter2015-06-241-9/+13
* drm/i915/psr: Restrict buffer tracking to the PSR pipeDaniel Vetter2015-06-241-4/+7
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