| Commit message (Expand) | Author | Age | Files | Lines |
* | intel_th: pci: Add Lunar Lake support | Alexander Shishkin | 2024-05-04 | 1 | -0/+5 |
* | intel_th: pci: Add Meteor Lake-S CPU support | Alexander Shishkin | 2024-05-04 | 1 | -0/+5 |
* | intel_th: pci: Add Meteor Lake-S support | Alexander Shishkin | 2024-05-04 | 1 | -0/+5 |
* | intel_th: pci: Add Sapphire Rapids SOC support | Alexander Shishkin | 2024-05-04 | 1 | -0/+5 |
* | intel_th: pci: Add Granite Rapids SOC support | Alexander Shishkin | 2024-05-04 | 1 | -0/+5 |
* | intel_th: pci: Add Granite Rapids support | Alexander Shishkin | 2024-05-04 | 1 | -0/+5 |
* | intel_th: pci: Add Raptor Lake-S CPU support | Alexander Shishkin | 2022-07-08 | 1 | -0/+5 |
* | intel_th: pci: Add Raptor Lake-S PCH support | Alexander Shishkin | 2022-07-08 | 1 | -0/+5 |
* | intel_th: pci: Add Meteor Lake-P support | Alexander Shishkin | 2022-07-08 | 1 | -0/+5 |
* | intel_th: Fix a resource leak in an error handling path | Christophe JAILLET | 2022-07-08 | 1 | -2/+8 |
* | intel_th: pci: Add Alder Lake-M support | Alexander Shishkin | 2021-04-16 | 1 | -0/+5 |
* | intel_th: pci: Add Rocket Lake CPU support | Alexander Shishkin | 2021-04-16 | 1 | -0/+5 |
* | intel_th: Constify all drvdata references | Alexander Shishkin | 2021-04-16 | 1 | -1/+1 |
* | intel_th: pci: Add Alder Lake-P support | Alexander Shishkin | 2021-01-21 | 1 | -0/+5 |
* | intel_th: pci: Add Alder Lake CPU support | Alexander Shishkin | 2020-10-05 | 1 | -0/+5 |
* | intel_th: pci: Add Alder Lake-S support | Alexander Shishkin | 2020-10-05 | 1 | -0/+5 |
* | intel_th: pci: Add Emmitsburg PCH support | Alexander Shishkin | 2020-07-10 | 1 | -0/+5 |
* | intel_th: pci: Add Tiger Lake PCH-H support | Alexander Shishkin | 2020-07-10 | 1 | -0/+5 |
* | intel_th: pci: Add Jasper Lake CPU support | Alexander Shishkin | 2020-07-10 | 1 | -0/+5 |
* | Merge 5.6-rc7 into char-misc-next | Greg Kroah-Hartman | 2020-03-23 | 1 | -0/+5 |
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| * | intel_th: pci: Add Elkhart Lake CPU support | Alexander Shishkin | 2020-03-18 | 1 | -0/+5 |
* | | intel_th: Disallow multi mode on devices where it's broken | Alexander Shishkin | 2020-03-18 | 1 | -2/+6 |
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* | intel_th: pci: Add Elkhart Lake SOC support | Alexander Shishkin | 2019-12-17 | 1 | -0/+5 |
* | intel_th: pci: Add Comet Lake PCH-V support | Alexander Shishkin | 2019-12-17 | 1 | -0/+5 |
* | intel_th: pci: Add Tiger Lake CPU support | Alexander Shishkin | 2019-11-20 | 1 | -0/+5 |
* | intel_th: pci: Add Ice Lake CPU support | Alexander Shishkin | 2019-11-20 | 1 | -0/+5 |
* | intel_th: pci: Add Jasper Lake PCH support | Alexander Shishkin | 2019-11-04 | 1 | -0/+5 |
* | intel_th: pci: Add Comet Lake PCH support | Alexander Shishkin | 2019-11-04 | 1 | -0/+5 |
* | intel_th: pci: Add Tiger Lake support | Alexander Shishkin | 2019-08-28 | 1 | -0/+5 |
* | intel_th: pci: Add support for another Lewisburg PCH | Alexander Shishkin | 2019-08-28 | 1 | -0/+5 |
* | intel_th: pci: Add Ice Lake NNPI support | Alexander Shishkin | 2019-07-03 | 1 | -0/+5 |
* | Merge tag 'char-misc-5.2-rc1-part2' of git://git.kernel.org/pub/scm/linux/ker... | Linus Torvalds | 2019-05-07 | 1 | -4/+28 |
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| * | intel_th: Only report useful IRQs to subdevices | Alexander Shishkin | 2019-05-03 | 1 | -0/+1 |
| * | intel_th: pci: Use MSI interrupt signalling | Alexander Shishkin | 2019-05-03 | 1 | -6/+10 |
| * | intel_th: Communicate IRQ via resource | Alexander Shishkin | 2019-05-03 | 1 | -2/+7 |
| * | intel_th: Add "rtit" source device | Alexander Shishkin | 2019-05-03 | 1 | -3/+8 |
| * | intel_th: Rework resource passing between glue layers and core | Alexander Shishkin | 2019-05-03 | 1 | -3/+12 |
* | | intel_th: pci: Add Comet Lake support | Alexander Shishkin | 2019-04-25 | 1 | -0/+5 |
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* | intel_th: pci: Add Ice Lake PCH support | Alexander Shishkin | 2018-09-18 | 1 | -0/+5 |
* | intel_th: Add SPDX GPL-2.0 header to replace GPLv2 boilerplate | Alexander Shishkin | 2018-03-28 | 1 | -9/+1 |
* | intel_th: pci: Add Lewisburg PCH support | Alexander Shishkin | 2017-09-22 | 1 | -0/+5 |
* | intel_th: pci: Add Cedar Fork PCH support | Alexander Shishkin | 2017-09-22 | 1 | -0/+5 |
* | intel_th: Perform time resync on capture start | Alexander Shishkin | 2017-08-25 | 1 | -3/+53 |
* | intel_th: pci: Use drvdata for quirks | Alexander Shishkin | 2017-08-25 | 1 | -1/+2 |
* | intel_th: pci: Add Cannon Lake PCH-LP support | Alexander Shishkin | 2017-08-25 | 1 | -0/+5 |
* | intel_th: pci: Add Cannon Lake PCH-H support | Alexander Shishkin | 2017-08-25 | 1 | -0/+5 |
* | intel_th: pci: Enable bus mastering | Alexander Shishkin | 2017-08-25 | 1 | -0/+2 |
* | intel_th: pci: Add Gemini Lake support | Alexander Shishkin | 2017-03-15 | 1 | -0/+5 |
* | intel_th: pci: Add Denverton SOC support | Alexander Shishkin | 2017-03-15 | 1 | -0/+5 |
* | intel_th: pci: Add Kaby Lake PCH-H support | Alexander Shishkin | 2016-07-14 | 1 | -0/+5 |