summaryrefslogtreecommitdiffstats
path: root/drivers/irqchip/irq-sifive-plic.c (follow)
Commit message (Expand)AuthorAgeFilesLines
* irqchip/sifive-plic: Unmask interrupt in plic_irq_enable()Nam Cao2024-10-081-10/+11
* irqchip/sifive-plic: Return error code on failureCharlie Jenkins2024-10-021-2/+6
* irqchip/sifive-plic: Add ACPI supportSunil V L2024-09-021-22/+77
* irqchip/sifive-plic: Probe plic driver early for Allwinner D1 platformAnup Patel2024-08-201-44/+71
* irqchip/sifive-plic: Chain to parent IRQ after handlers are readySamuel Holland2024-06-031-17/+17
* irqchip/sifive-plic: Avoid explicit cpumask allocation on stackDawei Li2024-04-241-5/+2
* Merge tag 'irq-msi-2024-03-10' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds2024-03-111-105/+170
|\
| * irqchip/sifive-plic: Improve locking safety by using irqsave/irqrestoreAnup Patel2024-02-231-6/+10
| * irqchip/sifive-plic: Parse number of interrupts and contexts early in plic_pr...Anup Patel2024-02-231-10/+33
| * irqchip/sifive-plic: Cleanup PLIC contexts upon irqdomain creation failureAnup Patel2024-02-231-20/+53
| * irqchip/sifive-plic: Use riscv_get_intc_hwnode() to get parent fwnodeAnup Patel2024-02-231-4/+5
| * irqchip/sifive-plic: Use devm_xyz() for managed allocationAnup Patel2024-02-231-33/+16
| * irqchip/sifive-plic: Use dev_xyz() in-place of pr_xyz()Anup Patel2024-02-231-11/+11
| * irqchip/sifive-plic: Convert PLIC driver into a platform driverAnup Patel2024-02-231-40/+61
* | irqchip/sifive-plic: Enable interrupt if needed before EOINam Cao2024-02-191-1/+7
|/
* irqchip/sifive-plic: Fix syscore registration for multi-socket systemsAnup Patel2023-10-271-3/+4
* irqchip/irq-sifive-plic: Add syscore callbacks for hibernationMason Huo2023-04-081-2/+91
* irqchip/sifive-plic: Support wake IRQsSamuel Holland2022-11-281-2/+4
* Merge tag 'riscv-for-linus-5.20-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2022-08-071-3/+4
|\
| * riscv: cpu: Add 64bit hartid support on RV64Sunil V L2022-07-201-3/+4
* | irqchip/sifive-plic: Separate the enable and mask operationsSamuel Holland2022-07-101-21/+34
* | irqchip/sifive-plic: Make better use of the effective affinity maskSamuel Holland2022-07-101-18/+9
* | irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handlingSamuel Holland2022-07-011-1/+1
* | irqchip/sifive-plic: Add support for Renesas RZ/Five SoCLad Prabhakar2022-07-011-4/+74
|/
* Merge tag 'irqchip-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/maz...Thomas Gleixner2022-03-141-12/+26
|\
| * irqchip/sifive-plic: Disable S-mode IRQs if running in M-modeNiklas Cassel2022-03-021-5/+19
| * irqchip/sifive-plic: Improve naming scheme for per context offsetsNiklas Cassel2022-03-021-7/+7
* | irqchip/sifive-plic: Add missing thead,c900-plic match stringGuo Ren2022-02-021-0/+1
|/
* irqchip/sifive-plic: Fixup EOI failed when maskedGuo Ren2021-11-121-1/+7
* irqchip: Bulk conversion to generic_handle_domain_irq()Marc Zyngier2021-06-101-5/+3
* irqchip/sifive-plic: Mark two global variables __ro_after_initJisheng Zhang2021-04-071-2/+2
* irqchip/sifive-plic: Fix chip_data access within a hierarchyGreentime Hu2020-11-011-4/+4
* irqchip/sifive-plic: Fix broken irq_set_affinity() callbackGreentime Hu2020-10-251-1/+1
* irqchip: RISC-V per-HART local interrupt controller driverAnup Patel2020-06-101-9/+23
* RISC-V: Rename and move plic_find_hart_id() to arch directoryAnup Patel2020-06-101-15/+1
* irqchip/sifive-plic: Improve boot prints for multiple PLIC instancesAnup Patel2020-05-251-2/+2
* irqchip/sifive-plic: Setup cpuhp once after boot CPU handler is presentAnup Patel2020-05-251-2/+12
* irqchip/sifive-plic: Set default irq affinity in plic_irqdomain_map()Anup Patel2020-05-251-0/+3
* irqchip/sifive-plic: Remove incorrect requirement about number of irq contextsWesley W. Terpstra2020-05-181-2/+0
* irqchip/sifive-plic: Fix maximum priority threshold valueAtish Patra2020-04-171-1/+1
* irqchip/sifive-plic: Add support for multiple PLICsAtish Patra2020-03-161-30/+51
* irqchip/sifive-plic: Enable/Disable external interrupts upon cpu online/offlineAtish Patra2020-03-161-4/+34
* Merge tag 'irqchip-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/...Thomas Gleixner2020-01-241-4/+26
|\
| * irqchip/sifive-plic: Support irq domain hierarchyYash Shah2020-01-201-4/+26
* | riscv: prefix IRQ_ macro names with an RV_ namespacePaul Walmsley2020-01-051-1/+1
|/
* riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig2019-11-051-4/+7
* Merge tag 'irqchip-fixes-5.4-2' of git://git.kernel.org/pub/scm/linux/kernel/...Thomas Gleixner2019-10-251-2/+2
|\
| * irqchip/sifive-plic: Skip contexts except supervisor in plic_init()Alan Mikhak2019-10-251-2/+2
* | Merge tag 'irqchip-fixes-5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/...Thomas Gleixner2019-10-141-14/+15
|\|
| * irqchip/sifive-plic: Switch to fasteoi flowMarc Zyngier2019-09-181-14/+15
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-13 10:43:02 +0100