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path: root/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h (follow)
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* ath9k: Remove set but not used variableLi Heng2020-09-291-21/+0
| | | | | | | | | | | | | | | | | | This addresses the following gcc warning with "make W=1": drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h:1331:18: warning: ‘ar9580_1p0_pcie_phy_clkreq_enable_L1’ defined but not used [-Wunused-const-variable=] drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h:1338:18: warning: ‘ar9580_1p0_pcie_phy_clkreq_disable_L1’ defined but not used [-Wunused-const-variable=] drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h:1345:18: warning: ‘ar9580_1p0_pcie_phy_pll_on_clkreq’ defined but not used [-Wunused-const-variable=] Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Li Heng <liheng40@huawei.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1600831531-8573-1-git-send-email-liheng40@huawei.com
* ath9k: Update AR9580 initvalsMiaoqing Pan2016-03-111-2/+2
| | | | | | | | | HW peak detect calibration would fail for AR9300 chips and we went for implementing the SW way of doing it instead of HW doing the peak detect calibration. Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath9k: Update AR9580 initvalsSujith Manoharan2014-10-271-1/+143
| | | | | | | This fixes RX sensitivity issues with AR9580. Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
* ath9k_hw: update ar9300 initvalsRajkumar Manoharan2014-04-301-1/+1
| | | | | | | | * rfsat gainchange hysteresis of rf_gain stuck with large interference present. Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
* ath9k: Add initval arrays for DFS channelsSujith Manoharan2013-12-091-2/+11
| | | | | Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
* ath9k: Fix initvals for freq 2484Sujith Manoharan2013-12-021-1/+1
| | | | | | | This is missing for AR9300, AR9580 and AR9340. Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
* ath9k: Update initvals for AR9580 v1.0Sujith Manoharan2013-12-021-173/+386
| | | | | Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
* ath9k: Remove duplicate initvals for AR9462 v2.1Sujith Manoharan2013-12-021-1/+1
| | | | | | | | | The initvals for AR9462 v2.1 are very similar to v2.0. Identify duplicate arrays and reuse the values from v2.0 to reduce module size. Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
* ath9k_hw: change AR9580 initvals to fix a stability issueFelix Fietkau2013-04-121-1/+1
| | | | | | | | | | | The hardware parsing of Control Wrapper Frames needs to be disabled, as it has been causing spurious decryption error reports. The initvals for other chips have been updated to disable it, but AR9580 was left out for some reason. Cc: stable@vger.kernel.org Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
* ath9k_hw: add tx gain tables for newer devicesFelix Fietkau2013-01-111-0/+76
| | | | | | | | Improves stability on affected devices and also fixes the Tx IQ calibration related regression on some AR9340 devices such as the TP-Link TL-WDR4300. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
* ath9k: de-duplicate initvalsFelix Fietkau2012-06-281-762/+10
| | | | | | | | | | | The initvals tool from https://github.com/mcgrof/qca-swiss-army-knife has been modified to detect identical initval tables and replace them with macros. This patch contains the generated changes. On MIPS this reduces the binary size by 24 KB with no runtime changes. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
* ath9k_hw: add AR9580 supportLuis R. Rodriguez2011-08-261-0/+1673
Here are the AR9580 1.0 initvals checksums using the Atheros initvals-tools [1]. This is useful for when we udate the initvals again with other values. It ensures that we match the same initvals used internally. The tool is documented on the wiki [2]. $ ./initvals -f ar9580-1p0 0x00000000e912711f ar9580_1p0_modes_fast_clock 0x000000004a488fc7 ar9580_1p0_radio_postamble 0x00000000f3888b02 ar9580_1p0_baseband_core 0x0000000003f783bb ar9580_1p0_mac_postamble 0x0000000094be244a ar9580_1p0_low_ob_db_tx_gain_table 0x0000000094be244a ar9580_1p0_high_power_tx_gain_table 0x0000000090be244a ar9580_1p0_lowest_ob_db_tx_gain_table 0x00000000ed9eaac6 ar9580_1p0_baseband_core_txfir_coeff_japan_2484 0x00000000c4d66d1b ar9580_1p0_mac_core 0x00000000e8e9043a ar9580_1p0_mixed_ob_db_tx_gain_table 0x000000003521a300 ar9580_1p0_wo_xlna_rx_gain_table 0x00000000301fc841 ar9580_1p0_soc_postamble 0x00000000a9a06b3a ar9580_1p0_high_ob_db_tx_gain_table 0x00000000a15ccf1b ar9580_1p0_soc_preamble 0x0000000029495000 ar9580_1p0_rx_gain_table 0x0000000037ac0ee8 ar9580_1p0_radio_core 0x00000000603a1b80 ar9580_1p0_baseband_postamble 0x000000003d8b4396 ar9580_1p0_pcie_phy_clkreq_enable_L1 0x00000000398b4396 ar9580_1p0_pcie_phy_clkreq_disable_L1 0x00000000397b4396 ar9580_1p0_pcie_phy_pll_on_clkreq [1] git://git.kernel.org/pub/scm/linux/kernel/git/mcgrof/initvals-tool.git [2] http://wireless.kernel.org/en/users/Drivers/ath9k_hw/initvals-tool Cc: David Quan <dquan@qca.qualcomm.com> Cc: Kathy Giori <kgiori@qca.qualcomm.com> Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com> Tested-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-21 02:49:47 +0100