summaryrefslogtreecommitdiffstats
path: root/drivers/net/wireless/realtek/rtw88/rtw8723d.c (follow)
Commit message (Collapse)AuthorAgeFilesLines
* wifi: rtw88: usb: Further limit the TX aggregationBitterblue Smith2024-06-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the number of frames sent to the chip in a single USB Request Block is limited only by the size of the TX buffer, which is 20 KiB. Testing reveals that as many as 13 frames get aggregated. This is more than what any of the chips would like to receive. RTL8822CU, RTL8822BU, and RTL8821CU want at most 3 frames, and RTL8723DU wants only 1 frame per URB. RTL8723DU in particular reliably malfunctions during a speed test if it receives more than 1 frame per URB. All traffic seems to stop. Pinging the AP no longer works. Fix this problem by limiting the number of frames sent to the chip in a single URB according to what each chip likes. Also configure RTL8822CU, RTL8822BU, and RTL8821CU to expect 3 frames per URB. RTL8703B may or may not be found in USB devices. Declare that it wants only 1 frame per URB, just in case. Tested with RTL8723DU and RTL8811CU. Cc: stable@vger.kernel.org Signed-off-by: Bitterblue Smith <rtl8821cerfe2@gmail.com> Acked-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/cb46ea35-7e59-4742-9c1f-01ceeaad36fb@gmail.com
* wifi: rtw88: Shared module for rtw8723x devicesFiona Klute2024-03-141-632/+41
| | | | | | | | | | | | | The already supported 8723d chip is very similar to 8703b/8723cs, split code that can be shared into a new module. The spec definition tables are combined into a struct so we only need one EXPORT_SYMBOL for them all. Acked-by: Ping-Ke Shih <pkshih@realtek.com> Tested-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Fiona Klute <fiona.klute@gmx.de> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://msgid.link/20240311103735.615541-2-fiona.klute@gmx.de
* wifi: rtw88: use struct instead of macros to set TX descPo-Hao Huang2023-06-211-2/+4
| | | | | | | | | | Remove macros that set TX descriptors. Use struct and le32_encode_bits() with mask definitions. Signed-off-by: Po-Hao Huang <phhuang@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20230616125540.36877-2-pkshih@realtek.com
* wifi: rtw88: rtw8723d: Implement RTL8723DS (SDIO) efuse parsingMartin Blumenstingl2023-05-251-0/+9
| | | | | | | | | | | The efuse of the SDIO RTL8723DS chip has only one known member: the mac address is at offset 0x11a. Add a struct rtw8723ds_efuse describing this and use it for copying the mac address when the SDIO bus is used. Reviewed-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20230522202425.1827005-3-martin.blumenstingl@googlemail.com
* wifi: rtw88: 8822c: extend reserved page numberPo-Hao Huang2023-04-201-0/+1
| | | | | | | | | | | | Extend 8822c's reserved page number to accommodate additional required pages. Reserved page is an area of memory in the FIFO dedicated for special purposes. Previously only one interface is supported so 8 pages should suffice, extend it so we can support 2 interfaces concurrently. Signed-off-by: Po-Hao Huang <phhuang@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20230414121135.17828-4-pkshih@realtek.com
* wifi: rtw88: Add rtw8723du chipset supportSascha Hauer2022-12-081-0/+28
| | | | | | | | | Add support for the rtw8723du chipset based on https://github.com/ulli-kroll/rtw88-usb.git Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20221202081224.2779981-12-s.hauer@pengutronix.de
* wifi: rtw88: 8822c: extend supported probe request sizePo-Hao Huang2022-08-091-1/+2
| | | | | | | | | | | | | | Some WSC IEs require size larger than we current supports. Extend size to fit those demands. Separate the registered scan IE length by IC so settings can be independent. Since old firmware uses fewer page number, define a firmware feature to be compatible with various firmware version. Signed-off-by: Po-Hao Huang <phhuang@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220727065003.28340-2-pkshih@realtek.com
* wifi: rtw88: Fix Sparse warning for rtw8723d_hw_specLarry Finger2022-05-301-1/+1
| | | | | | | | | | | | | | | | | Sparse lists the following: CHECK drivers/net/wireless/realtek/rtw88/rtw8723d.c drivers/net/wireless/realtek/rtw88/rtw8723d.c:2704:22: warning: symbol 'rtw8723d_hw_spec' was not declared. Should it be static? The warning arises because the external declaration for rtw8723d_hw_spec occurs in rtw8723de.h, which is not included in rtw8723d.h. That line is moved, and the now empty file rtw8723de.h is deleted. Symbol 'rtw8723d_hw_spec' can be made constant. Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220524153621.19027-4-Larry.Finger@lwfinger.net
* rtw88: add HT MPDU density value for each chipChih-Kang Chang2022-05-011-0/+1
| | | | | | | | | | Each chip have best ampdu density value, the correct setting can improve throughput performance. Signed-off-by: Chih-Kang Chang <gary.chang@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220428020521.8015-1-pkshih@realtek.com
* rtw88: coex: Add WLAN MIMO power saving for Bluetooth gaming controllerChing-Te Ku2022-02-211-0/+1
| | | | | | | | | | | | | To keep high sensitivity reaction, Bluetooth gaming controller will send packet very frequently, it will make WLAN performance very poor. To solve this situation, MIMO PS mechanism makes WLAN/BT own an antenna itself, WLAN quits 2SS performance but it can get a stable 1SS performance and Bluetooth gaming controller can keep sensitivity reaction at the same time. Signed-off-by: Ching-Te Ku <ku920601@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220215004855.4098-5-pkshih@realtek.com
* rtw88: 8723de: adjust the LTR settingChin-Yen Lee2021-01-251-2/+2
| | | | | | | | | | | | | | The LTR mechanism enables PCIE Endpoints to report the service latency requirements and CPU will enter appropriate sleep state to save power based on the LTR value. 8723de provides two registers to config the LTR, and the original setting is too short for CPU to ente sleep state. The patch adjust the LTR setting. Signed-off-by: Chin-Yen Lee <timlee@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20210113014342.3615-1-pkshih@realtek.com
* rtw88: coex: upgrade coexistence A2DP mechanismChing-Te Ku2020-12-021-0/+1
| | | | | | | | | | | | Add modifications for A2DP interoperability issue of TWS earphones. Some TWS earphones has low buffer size, so it's necessary to reduce the slot period to let it get data more frequently. (e.g. use 4-slot to replace the original 2-slot method). Signed-off-by: Ching-Te Ku <ku920601@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20201126021059.11981-10-pkshih@realtek.com
* rtw88: add CCK_PD debug logPing-Ke Shih2020-11-241-0/+12
| | | | | | | | In order to help debugging in field, we add some log messages. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20201109090123.9254-2-pkshih@realtek.com
* rtw88: 8723d: add cck pd seetingsPing-Ke Shih2020-11-241-0/+18
| | | | | | | | | | | | | | CCK PD can reduce the number of false alarm of the CCK rates. It dynamically adjusts the power threshold and CS ratio. The values are compared to the values of the previous level, if the level is changed, set new values of power threshold and CS ratio. Implement rtw_chip_ops::cck_pd_set() for 8723d. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20201109090123.9254-1-pkshih@realtek.com
* rtw88: coex: update coex parameter to improve A2DP qualityChing-Te Ku2020-11-101-29/+29
| | | | | | | | | | | | Update COEX parameters and logic to enhance WL/BT performance while WL_Busy + A2DP in a less interference environment. It can avoid the interference comes cross from each other and earned more performance. Signed-off-by: Ching-Te Ku <ku920601@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20201109085909.9143-3-pkshih@realtek.com
* rtw88: coex: fixed some wrong register definition and settingChing-Te Ku2020-11-101-2/+2
| | | | | | | | | | | | | Some register definition and bit definition were incorrect. e.g. REG_BT_COEX_V2 should be word alignment to meet the coding style. e.g. set REG_BT_TDMA_TIME[5:0]=0x5, But the original is to set REG_BT_TDMA_TIME[7:0]=0x5. This will cause unexpected hardware behavior. Signed-off-by: Ching-Te Ku <ku920601@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20201109085909.9143-2-pkshih@realtek.com
* rtw88: coex: separate BLE HID profile from BLE profileChing-Te Ku2020-11-071-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | BT firmware will report BLE-HID and BLE-RCU in different profile. We can distinguish the two profile from BT info now. Add the coexistence for BLE-HID coexistence, it can make BLE HID work more smoothly. BLE-HID need to Tx/Rx packet more frequently to respond user operation, but RCU doesn't. In the case of RCU coexistence, it will make Wi-Fi have a higher priority to earn more Wi-Fi throughput. If BLE-HID go for the same case, it will make user feel mouse is lagging. Desired BT firmware BT-COEX version: 0x1c Desired WL firmware version: 9.9 Signed-off-by: Ching-Te Ku <ku920601@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20201030055506.6560-1-pkshih@realtek.com
* rtw88: coex: Fix ACL Tx pause during BT inquiry/page.Zong-Zhe Yang2020-07-151-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a set of logic with corresponding coexistence parameters to handle the situation under BT inquiry/page. We will set PSTDMA while WL-Busy + BT inquiry/page to separate WL/BT slots. PSTDMA can protect WL data rate and BT performance. If WL-Busy + BT inquiry/page and there was BT device paired, We will set the mechanism to 4Slot PSTDMA. In 4Slot PSTDMA, the paired devices can perform more smoothly and prevent some issues trigger from insufficient data. And to avoid A2DP glitch or disconnection, we will adjust ACL data priority higher than inquiry/page. In addition, we found sometimes BT inquiry/page still working last for seconds after BT had notified inquiry/page finished. It will lead to A2DP glitch cause of ACL data, inquiry/page priority toggled. To fix the corner, we add a timer to remain the inquiry/page status. And we found WL busy/idle threshold is too sensitive, it will keep switching in some weak network environment and coexistence mechanism will switch between TDMA and PSTDMA. The very frequently switching may destroyed not only the handshake with AP, but BT performance. And it will trigger some unexpected error. To prevent the frequently switching, we add a timer to delay the status change while WL busy switch to idle. Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200715023324.8600-1-yhchuang@realtek.com
* rtw88: coex: 8723d: handle BT inquiry casesPing-Ke Shih2020-05-291-2/+3
| | | | | | | | | | | | | | | | Coex mechanism used to make BT have higher priority and more time to transfer data when BT inquiry-page, which leads to poor WiFi performance. Should take WiFi traffic into consideration. If the WiFi is having heavy traffic, use another parameter to make sure WiFi has more chance to TX/RX, while guarantee the priority of BT for inquiry. If the WiFi isn't busy (connected or not), set proper parameter to fix originals. Fixes: f5df1a8b4376 ("rtw88: 8723d: Add 8723DE to Kconfig and Makefile") Tested-by: You-Sheng Yang <vicamo.yang@canonical.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200529025009.2468-3-yhchuang@realtek.com
* rtw88: coex: 8723d: set antanna control ownerPing-Ke Shih2020-05-291-0/+5
| | | | | | | | | | | | | | Without setting antenna control owner, the WiFi could be disconnected if the BT has traffic. Because the antenna is switched to BT side for its traffic, and the WiFi will have no chance to transfer data. Set control owner to prevent WiFi disconnect issue. Fixes: f5df1a8b4376 ("rtw88: 8723d: Add 8723DE to Kconfig and Makefile") Tested-by: You-Sheng Yang <vicamo.yang@canonical.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200529025009.2468-2-yhchuang@realtek.com
* Revert "rtw88: no need to set registers for SDIO"Yan-Hsuan Chuang2020-05-291-0/+40
| | | | | | | | | | | | | | | | | This reverts commit 07d0f5534935e2daf63a4e1012af13d68e089fed. For rtw88 driver, the SDIO is going to be supported, so there is no need to remove the SDIO related power sequence settings. And while the power sequence parser will pass in the mask of the HCI, the SDIO part will not be used to set registers accordingly. Moreover, the power sequence table is released as a whole package, so the next time if we are going to update, the SDIO settings will be overwritten. So, revert this now. Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200520055350.23328-1-yhchuang@realtek.com
* rtw88: no need to set registers for SDIOKevin Lo2020-05-181-40/+0
| | | | | | | | There's no need to set SDIO related registers when powering up/down the chip. Signed-off-by: Kevin Lo <kevlo@kevlo.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200515061153.GA15714@ns.kevlo.org
* rtw88: 8723d: fix incorrect setting of ldo_pwrColin Ian King2020-05-181-1/+1
| | | | | | | | | | | | | | Currently ldo_pwr has the LDO25 voltage bits set to zero and then it is overwritten with the new voltage setting. The assignment looks incorrect, it should be bit-wise or'ing in the new voltage setting rather than a direct assignment. Addresses-Coverity: ("Unused value") Fixes: 1afb5eb7a00d ("rtw88: 8723d: Add cfg_ldo25 to control LDO25") Signed-off-by: Colin Ian King <colin.king@canonical.com> Acked-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200514181329.16292-1-colin.king@canonical.com
* rtw88: extract: make 8723d an individual kernel moduleZong-Zhe Yang2020-05-181-0/+5
| | | | | | | | | | | | | | | Make objects about 8723d functions and 8723d tables, i.e. rtw8723d.o and rtw8723d_table.o, an individual kernel module called rtw88_8723d.ko. For 8723d pcie chip, i.e. 8723DE chip, add a chip entry point module called rtw88_8723de.ko which will depend on rtw88_8723d.ko and rtwpci.ko. Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200515052327.31874-6-yhchuang@realtek.com
* rtw88: 8723d: fix sparse warnings for power trackingYan-Hsuan Chuang2020-05-131-1/+1
| | | | | | | | | | | | sparse warnings: (new ones prefixed by >>) >> drivers/net/wireless/realtek/rtw88/rtw8723d.c:1899:6: sparse: sparse: symbol 'rtw8723d_pwr_track' was not declared. Should it be static? Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200512103534.5889-1-yhchuang@realtek.com
* rtw88: 8723d: Add coex supportPing-Ke Shih2020-05-131-0/+327
| | | | | | | | | | | | | 8723D is a Wifi+BT combo card. To make them work properly, we need coex mechanism to avoid interference, such as TX simultaneously. Basically, coex.c provide main algorithm to deal with many use cases, and this commit adds some parameters and ops differ from other chips, because coex hardware and WiFi generation are changed. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200512102621.5148-8-yhchuang@realtek.com
* rtw88: 8723d: set ltecoex register address in chip_infoPing-Ke Shih2020-05-131-0/+7
| | | | | | | | | | | Since 8723D use different address of ltecoex register, this commit add a new field in chip_info and fill proper address. Then, ltecoex_read_reg() and ltecoex_reg_write() can use them to access ltecoex according to chip. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200512102621.5148-7-yhchuang@realtek.com
* rtw88: 8723d: implement flush queuePing-Ke Shih2020-05-131-0/+17
| | | | | | | | | | | | Flush queue is used to check if queue is empty, before doing something else. Since 8723D uses different registers and page number of availabl/reserved occupy 8 bits instead of 16 bits, so use a 'wsize' field to discriminate which rtw_read{8,16} is adopted. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200512102621.5148-6-yhchuang@realtek.com
* rtw88: 8723d: Add shutdown callback to disable BT USB suspendPing-Ke Shih2020-05-131-0/+6
| | | | | | | | | | | | Without this patch, wifi card can't initialize properly due to BT in USB suspend state. So, we disable BT USB suspend (wakeup) in shutdown callback that is the moment before rebooting. To save BT USB power, we can't do this in 'remove' callback. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200512102621.5148-5-yhchuang@realtek.com
* rtw88: 8723d: Add power trackingPing-Ke Shih2020-05-131-0/+400
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When chip's temperature is changed, RF characters are changed. To keep the characters to be consistent, 8723d uses thermal meter to assist in calibrating LCK, IQK, crystal and TX power. A base thermal value is programmed in efuse, all calibration data in MP process is based on this thermal value. So we calucate the delta of thermal value between the base value, and use this delta to reference XTAL and TX power offset tables to know how much we need to adjust. For IQK and LCK, driver checks if delta of thermal value is over 8, then they are triggered. For crystal adjustment, when delta of thermal value is changed, we check XTAL tables to get offset of XTAL value. If thermal value is larger than base value, positive table (_p as suffix) is used. Otherwise, we use negative table (_n as suffix). Then, we add offset to XTAL default value programmed in efuse, and write sum value to register. To compensate TX power, there are two hierarchical tables. First level use delta of thermal value to access eight tables to yield delta of TX power index. Then, plus base TX power index to get index of BB swing table (second level tables) where register value is induced. BB swing table can't deal with all cases, if index of BB swing table is over the size of the table. In this case, TX AGC is used to compensate the remnant part. Assume 'upper' is the upper bound of BB swing table, and 'target' is the desired index. Then, we can illustrate them as compensation method BB swing TX AGC ------------------- -------- -------------- target > upper upper target - upper target < 0 0 target otherwise target 0 For debug purpose, add a column 'rem' to tx_pwr_tbl entry, and it looks like path rate pwr base (byr lmt ) rem A CCK_1M 32(0x20) 34 -2 ( 0 -2) 0 Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200512102621.5148-4-yhchuang@realtek.com
* rtw88: 8723d: add IQ calibrationPing-Ke Shih2020-05-131-0/+817
| | | | | | | | | | | | | | | | | | | | | | | | | | | IQ calibration is used to calibrate RF characteristic to yield expected performance. Basically, we do calibration twice and compare the similarity to determine calibration is good or not, if not we do the third calibration, and then compare with the results of first and second calibration. If it still not similar, IQK is failed. Before doing calibration, we need to backup registers that will be modified in calibration procedure, and restore these registers after calibration is done. A calibration procedure can divided into four sub-procedures that are S1-TX, S1-RX, S0-TX and S0-RX. Where, S1 and S0 represent to path A and B respectively. Each sub-procedure configure proper registers, and then rigger one-shot calibration and poll until completion. For RX calibration, it needs to do twice one-shot calibration, first one is to yield parameter used by second one. The result of TX part is stored for TX power tracking that adjusts TX AGC to output expected power. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200512102621.5148-3-yhchuang@realtek.com
* rtw88: 8723d: Add LC calibrationPing-Ke Shih2020-05-131-0/+31
| | | | | | | | | | LC calibration is done by hardware circuit. Driver sets the LCK bit to kick start, and then poll the bit to check if it's done. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200512102621.5148-2-yhchuang@realtek.com
* rtw88: 8723d: add interface configurations tablePing-Ke Shih2020-05-061-0/+21
| | | | | | | | | | | Interface configuration table is used to configure PCI PHY that are normally decided by design or bootstrap pin, and driver can do additional settings by this table. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200504105010.10780-9-yhchuang@realtek.com
* rtw88: 8723d: Set IG register for CCK ratePing-Ke Shih2020-05-061-0/+5
| | | | | | | | | | DIG sets only one IG register for most chips, but 8723D need to set additional register for CCK rate. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200504105010.10780-8-yhchuang@realtek.com
* rtw88: 8723d: Add chip_ops::false_alarm_statisticsPing-Ke Shih2020-05-061-0/+65
| | | | | | | | | | | | | | This ops is used to do statistics of false alarm periodically, and then fine tune RX initial gain to adaptive different circumstance. There are three steps, hold/get/reset counter, to retrieve false alarm counters that consist of CCK and OFDM. In addition to false alarm counters, it also collects CRC ok/error counters of CCK, OFDM and HT. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200504105010.10780-7-yhchuang@realtek.com
* rtw88: 8723d: some chips don't support LDPCPing-Ke Shih2020-05-061-0/+1
| | | | | | | | | | | Some chips are not able to receive LDPC packets. Add an attribute to rtw_chip_info to determine if the LDPC capability in [ht/vht]_cap should be advertised or not. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200504105010.10780-6-yhchuang@realtek.com
* rtw88: 8723d: Add set_channelPing-Ke Shih2020-05-061-0/+161
| | | | | | | | | | | | | | | | | Set MAC/BB/RF register according to specified channel. The function rtw_set_channel_mac() is used to set MAC registers, but 8723D only need some of them. For channel 14, we need to set different CCK DFIR values, so restore the values when channel 1 to 13 is selected. Spur calibration is needed in channel 13 and 14, and we do notch if spur is over threshold. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200504105010.10780-4-yhchuang@realtek.com
* rtw88: 8723d: Add query_rx_descPing-Ke Shih2020-05-061-0/+116
| | | | | | | | | | | | | | | | This ops is used to parse RX descriptor to know the length of received packet and containing PHY status. If PHY status is existing, the order is RX descriptor, PHY status and then packet. There are two types of PHY status, named CCK and OFDM. Their size are the same, but formats are different. struct ieee80211_rx_status is also filled depends on above information. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200504105010.10780-3-yhchuang@realtek.com
* rtw88: 8723d: Add DIG parameterPing-Ke Shih2020-05-061-0/+7
| | | | | | | | | | | To improve user experience in field, we need DIG to adjust RX initial gain depends on field situation. Since each chip has its own register address, this commit defines 8723d specific address. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200504105010.10780-2-yhchuang@realtek.com
* rtw88: 8723d: initialize mac/bb/rf basic functionsPing-Ke Shih2020-04-231-0/+124
| | | | | | | | | | | | Implement rtw_chip_ops::phy_set_param and ::mac_init to initialize mac/bb/rf, and they are used during interface up. The procedure contains power on sequence registers, download firmware, load predefined parameters, mac/bb/rf specific register and etc. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200422034607.28747-9-yhchuang@realtek.com
* rtw88: 8723d: Organize chip TX/RX FIFOPing-Ke Shih2020-04-231-0/+31
| | | | | | | | | | | | | | | | | | | | | | TX FIFO size is 32k and it was divided into 256 pages with 128 bytes. A boundary is used to split pages into two parts, head part is used to store TX packets coming from host, and tail part is reserved for special purposes, such as beacon packet, null data packet and so on. The TX packets coming from host have many categories, such as VO, VI, BE, BK, MG and etc. When going into head part of TX FIFO, they are classified to four priority queue named low, normal, high and extra priority queues. Each priority queue occupies predefined number of page, if a certain priority queue is full, TX packet will store into PUB priority queue. Similarly, RX FIFO is 16k and split into two parts, head part is used to store RX packets, and tail part is 128 bytes and used to store report. Thus, we fill this boundary to register as well. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200422034607.28747-8-yhchuang@realtek.com
* rtw88: 8723d: implement set_tx_power_index opsPing-Ke Shih2020-04-231-0/+61
| | | | | | | | | | | | The txagc table is used to map rate_id and txagc register address and mask, and ops set_tx_power_index uses this table to write TX power to corresponding registers. Since 8723D is a 1x1 2.4G 11n chip, only CCK, OFDM and HT_MCS 0-7 are listed in the table. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200422034607.28747-7-yhchuang@realtek.com
* rtw88: add legacy firmware download for 8723D devicesPing-Ke Shih2020-04-231-0/+1
| | | | | | | | | | | | | | | | | | The WLAN CPU of 8723D device is different from others, add legacy firmware download function for it. A new variable wlan_cpu is used to decide which firmware download function we should use. Legacy firmware file contains 32 bytes header including version and subversion. When downloading to wlan cpu, header is excluded. Firmware is downloaded via beacon queue to reserved page that is a part of TX buffer. Since 11N WLAN CPU uses different control registers, this patch introduces related control registers. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200422034607.28747-2-yhchuang@realtek.com
* rtw88: 8723d: Add read_efuse to recognize efuse info from mapPing-Ke Shih2020-04-211-0/+43
| | | | | | | | | | | | The logical efuse map is decoded from physical map by parsing the header format of the physical map. And each different type of chips has different logical efuse layout. So add the logical map's layout for parsing the efuse contents. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200420055054.14592-9-yhchuang@realtek.com
* rtw88: 8723d: Add new chip op efuse_grant() to control efuse accessPing-Ke Shih2020-04-211-0/+13
| | | | | | | | | | 8723D devices need to grant efuse access before dumping physical efuse map, other chips don't need it, so keep this ops as blank. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200420055054.14592-8-yhchuang@realtek.com
* rtw88: 8723d: Add cfg_ldo25 to control LDO25Ping-Ke Shih2020-04-211-0/+15
| | | | | | | | | | Implement rtw_chip_ops::cfg_ldo25 to enable/disable LDO25 with proper voltage. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200420055054.14592-7-yhchuang@realtek.com
* rtw88: 8723d: Add mac/bb/rf/agc/power_limit tablesPing-Ke Shih2020-04-211-0/+11
| | | | | | | | | | | Add corresponding parameter tables for 8723D devices. Since 8723D devices currently have only one RFE type, there is only one entry in rtw8723d_rfe_defs. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200420055054.14592-6-yhchuang@realtek.com
* rtw88: 8723d: Add RF read/write opsPing-Ke Shih2020-04-211-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | 8723D use SIPI to indirectly read RF register instead of directly read, so introduce a new struct rtw_rf_sipi_addr and new function rtw_phy_read_rf_sipi(). Since other chips don't use the new function, only 8723D needs to fill struct rtw_rf_sipi_addr in rtw_chip_info. Because there are two kinds of functions for reading RF registers now, change rtw_phy_read_rf() to chip->ops->read_rf() in rtw_phy_write_rf_reg_sipi() so that we can switch tp proper RF read functions depends on the type of the chip. Though 8723D is an 1x1 chip, it has two RF PHY and we can switch to one of them, and that should be configured properly. Hence, add a fix_rf_phy_num to struct rtw_chip_info to allow driver to set one of the PHY's registers for 8723D, even it is only 1x1. Another variable rf_phy_num is introduced to keep the constraint number of RF path we can access, and its value is: rf_phy_num = (fix_rf_phy_num ? fix_rf_phy_num : rf_path_num) Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200420055054.14592-5-yhchuang@realtek.com
* rtw88: 8723d: Add power sequencePing-Ke Shih2020-04-211-0/+403
| | | | | | | | | Add corresponding power sequence for 8723D devices Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200420055054.14592-4-yhchuang@realtek.com
* rtw88: 8723d: add beamform wrapper functionsPing-Ke Shih2020-04-211-0/+3
| | | | | | | | | | | | | 8723D doesn't support beamform because rtw88 only supports VHT beamform but 8723d doesn't have VHT capability. Though 8723d doesn't support beamform, BSS_CHANGED_MU_GROUPS is still marked as changed when doing disassociation. So, add wrapper functions for all beamform ops to make sure they aren't NULL before calling. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200420055054.14592-3-yhchuang@realtek.com
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-25 12:59:19 +0100