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path: root/drivers/phy/cadence (follow)
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* phy: cadence-torrent: Add USXGMII(156.25MHz) + SGMII/QSGMII(100MHz) multilink...Swapnil Jakhade2024-02-071-0/+410
* phy: cadence-torrent: Add USXGMII(156.25MHz) + SGMII/QSGMII(100MHz) multilink...Swapnil Jakhade2024-02-071-0/+101
* phy: cadence-torrent: Add PCIe(100MHz) + USXGMII(156.25MHz) multilink configu...Swapnil Jakhade2024-02-071-9/+200
* phy: Explicitly include correct DT includesRob Herring2023-07-173-4/+2
* phy: cadence: Sierra: Add single link SGMII register configurationMarcin Wierzbicki2023-07-121-0/+98
* phy: cadence-torrent: Use key:value pair table for all settingsRoger Quadros2023-07-121-1176/+485
* phy: cadence-torrent: Add single link USXGMII configuration for 156.25MHz refclkSwapnil Jakhade2023-07-121-5/+228
* Merge tag 'phy-for-6.5_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/p...Linus Torvalds2023-07-062-202/+613
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| * phy: cadence: salvo: Add cdns,usb2-disconnect-threshold-microvolt propertyFrank Li2023-05-191-0/+29
| * phy: cadence: salvo: add .set_mode APIPeter Chen2023-05-191-0/+29
| * phy: cadence: salvo: add bist fixPeter Chen2023-05-191-0/+2
| * phy: cadence: salvo: decrease delay value to zero for txvalidPeter Chen2023-05-191-0/+17
| * phy: cadence: salvo: add access for USB2PHYPeter Chen2023-05-191-8/+10
| * phy: cadence-torrent: Add USB + DP multilink configurationSwapnil Jakhade2023-05-081-0/+98
| * phy: cadence-torrent: Add PCIe + DP multilink configuration for 100MHz refclkSwapnil Jakhade2023-05-081-57/+227
| * phy: cadence-torrent: Prepare driver for multilink DP supportSwapnil Jakhade2023-05-081-137/+168
| * phy: cadence-torrent: Add function to get PLL to be configured for DPSwapnil Jakhade2023-05-081-0/+33
* | phy: cadence: torrent: Add a determine_rate hookMaxime Ripard2023-06-091-0/+1
* | phy: cadence: sierra: Add a determine_rate hookMaxime Ripard2023-06-091-0/+1
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* phy: cadence: cdns-dphy-rx: Add common module reset supportSinthu Raja2023-04-121-0/+32
* phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configurationSwapnil Jakhade2023-04-121-2/+139
* phy: cadence: Sierra: Use clk_parent_data to provide parent informationLars-Peter Clausen2023-03-311-42/+15
* phy: cadence: Sierra: Replace `clk_register(`) with `clk_hw_register()`Lars-Peter Clausen2023-03-311-20/+26
* phy: cadence: phy-cadence-torrent: Convert to platform remove callback return...Uwe Kleine-König2023-03-201-4/+2
* phy: cadence: phy-cadence-sierra: Convert to platform remove callback returni...Uwe Kleine-König2023-03-201-4/+2
* phy: cadence: cdns-dphy: Convert to platform remove callback returning voidUwe Kleine-König2023-03-201-4/+2
* phy: cadence-torrent: Remove unused `regmap` field from state structLars-Peter Clausen2022-07-081-1/+0
* phy: cadence: Sierra: Remove unused `regmap` field from state structLars-Peter Clausen2022-07-081-1/+0
* phy: cdns-dphy: Add support for DPHY TX on J721eRahul T R2022-07-051-0/+61
* phy: cdns-dphy: Add band config for dphy txRahul T R2022-07-051-1/+39
* phy: cadence: Sierra: Add TI J721E specific PCIe multilink lane configurationSwapnil Jakhade2022-04-131-3/+190
* phy: cadence: Add Cadence D-PHY Rx driverPratyush Yadav2022-03-023-0/+264
* phy/cadence: Use of_device_get_match_data()Minghao Chi (CGEL ZTE)2022-02-251-6/+1
* phy: cadence: Sierra: Add support for skipping configurationAswath Govindraju2022-02-071-25/+57
* phy: cadence: Sierra: fix error handling bugs in probe()Dan Carpenter2022-01-241-14/+21
* phy: cadence: Sierra: Add support for derived reference clock outputSwapnil Jakhade2021-12-271-1/+108
* phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configurationSwapnil Jakhade2021-12-271-1/+376
* phy: cadence: Sierra: Add support for PHY multilink configurationsSwapnil Jakhade2021-12-271-8/+190
* phy: cadence: Sierra: Fix to get correct parent for mux clocksSwapnil Jakhade2021-12-271-5/+26
* phy: cadence: Sierra: Update single link PCIe register configurationSwapnil Jakhade2021-12-271-1/+213
* phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operationSwapnil Jakhade2021-12-271-1/+72
* phy: cadence: Sierra: Check cmn_ready assertion during PHY power onSwapnil Jakhade2021-12-271-0/+45
* phy: cadence: Sierra: Add PHY PCS common register configurationsSwapnil Jakhade2021-12-271-0/+38
* phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra ...Swapnil Jakhade2021-12-271-10/+11
* phy: cadence: Sierra: Add support to get SSC type from device treeSwapnil Jakhade2021-12-271-1/+5
* phy: cadence: Sierra: Prepare driver to add support for multilink configurationsSwapnil Jakhade2021-12-271-56/+139
* phy: cadence: Sierra: Use of_device_get_match_data() to get driver dataSwapnil Jakhade2021-12-271-9/+4
* phy: cadence-torrent: use swap() to make code cleanerYang Guang2021-11-231-4/+2
* phy: cadence-torrent: Add support to output received reference clockSwapnil Jakhade2021-10-261-11/+148
* phy: cadence-torrent: Model reference clock driver as a clock to enable deriv...Swapnil Jakhade2021-10-261-25/+132
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