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* Merge tag 'phy-for-6.13' of ↵Linus Torvalds5 days7-62/+206
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "New hardware support: - ST STM32MP25 combophy support - Sparx5 support for lan969x serdes and updates to driver to support this - NXP PTN3222 eUSB2 to USB2 redriver - Qualcomm SAR2130P eusb2 support, QCS8300 USB DW3 and QMP USB2 support, X1E80100 QMP PCIe PHY Gen4 support, QCS615 and QCS8300 QMP UFS PHY support and SA8775P eDP PHY support - Rockchip rk3576 usbdp and rk3576 usb2 phy support - Binding for Microchip ATA6561 can phy Updates: - Freescale driver updates from hdmi support - Conversion of rockchip rk3228 hdmi phy binding to yaml - Broadcom usb2-phy deprecated support dropped and USB init array update for BCM4908 - TI USXGMII mode support in J7200 - Switch back to platform_driver::remove() subsystem update" * tag 'phy-for-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (59 commits) phy: qcom: qmp: Fix lecacy-legacy typo phy: lan969x-serdes: add support for lan969x serdes driver dt-bindings: phy: sparx5: document lan969x phy: sparx5-serdes: add support for branching on chip type phy: sparx5-serdes: add indirection layer to register macros phy: sparx5-serdes: add function for getting the CMU index phy: sparx5-serdes: add ops to match data phy: sparx5-serdes: add constant for the number of CMU's phy: sparx5-serdes: add constants to match data phy: sparx5-serdes: add support for private match data phy: bcm-ns-usb2: drop support for old binding variant dt-bindings: phy: bcm-ns-usb2-phy: drop deprecated variant dt-bindings: phy: Add QMP UFS PHY compatible for QCS8300 dt-bindings: phy: qcom: snps-eusb2: Add SAR2130P compatible dt-bindings: phy: ti,tcan104x-can: Document Microchip ATA6561 phy: airoha: Fix REG_CSR_2L_RX{0,1}_REV0 definitions phy: airoha: Fix REG_CSR_2L_JCPLL_SDM_HREN config in airoha_pcie_phy_init_ssc_jcpll() phy: airoha: Fix REG_PCIE_PMA_TX_RESET config in airoha_pcie_phy_init_csr_2l() phy: airoha: Fix REG_CSR_2L_PLL_CMN_RESERVE0 config in airoha_pcie_phy_init_clk_out() phy: phy-rockchip-samsung-hdptx: Don't request RST_PHY/RST_ROPLL/RST_LCPLL ...
| * phy: phy-rockchip-samsung-hdptx: Don't request RST_PHY/RST_ROPLL/RST_LCPLLAndy Yan2024-10-171-16/+1
| | | | | | | | | | | | | | | | | | | | RST_PHY/RST_ROPLL/RST_LCPLL are used for debug only on rk3588, and they are not exported on rk3576, no need to request it in driver. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Link: https://lore.kernel.org/r/20240920093629.7410-1-andyshrk@163.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: Switch back to struct platform_driver::remove()Uwe Kleine-König2024-10-174-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After commit 0edb555a65d1 ("platform: Make platform_driver::remove() return void") .remove() is (again) the right callback to implement for platform drivers. Convert all platform drivers below drivers/phy/ to use .remove(), with the eventual goal to drop struct platform_driver::remove_new(). As .remove() and .remove_new() have the same prototypes, conversion is done by just changing the structure member name in the driver initializer. While touching these files, make indention of the struct initializer consistent in several files. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Link: https://lore.kernel.org/r/20241009065307.504930-2-u.kleine-koenig@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: rockchip: usbdp: add rk3576 device match dataFrank Wang2024-10-171-0/+41
| | | | | | | | | | | | | | | | | | | | This adds RK3576 device match data support. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Acked-by: Dragan Simic <dsimic@manjaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20241014020342.15974-2-frawang.cn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: rockchip: inno-usb2: Add usb2 phys support for rk3576William Wu2024-10-171-0/+103
| | | | | | | | | | | | | | | | | | | | | | The RK3576 SoC has two independent USB2.0 PHYs, and each PHY has one port. This adds device specific data for it. Signed-off-by: William Wu <william.wu@rock-chips.com> Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20241016073713.14133-4-frawang.cn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: rockchip: inno-usb2: convert clock management to bulkFrank Wang2024-10-171-8/+37
| | | | | | | | | | | | | | | | | | | | | | Since some Rockchip SoCs (e.g RK3576) have more than one clock, this converts the clock management from single to bulk method to make the driver more flexible. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20241016073713.14133-1-frawang.cn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: phy-rockchip-inno-usb2: Use dev_err_probe() in the probe pathDragan Simic2024-10-071-17/+10
| | | | | | | | | | | | | | | | | | | | Improve error handling in the probe path by using function dev_err_probe() instead of function dev_err(), where appropriate. Signed-off-by: Dragan Simic <dsimic@manjaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/d4ccd9fc278fb46ea868406bf77811ee507f0e4e.1725524803.git.dsimic@manjaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: phy-rockchip-inno-usb2: Handle failed extcon allocation betterDragan Simic2024-10-071-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Return the actual error code upon failure to allocate extcon device, instead of hardcoding -ENOMEM. Use dev_err_probe() to also log appropriate messages, which is fine because the containing function is used in the probe path. Helped-by: Heiko Stubner <heiko@sntech.de> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/cc4995aa3e569be6bc23ca126b41fba82d50eeee.1725524802.git.dsimic@manjaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: phy-rockchip-inno-usb2: Perform trivial code cleanupsDragan Simic2024-10-071-17/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | Perform a few trivial code cleanups, e.g. to obey the reverse Christmas tree rule, to avoid use of "{ ... }" code blocks where they aren't really needed, or to avoid line wrapping by using the 100-column width better. No intended functional changes are introduced by these code cleanups. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/adce7309f6fd9e1191c53bab552a8531d1a71216.1725524802.git.dsimic@manjaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: phy-rockchip-samsung-hdptx: Depend on CONFIG_COMMON_CLKCristian Ciocaltea2024-10-171-0/+1
|/ | | | | | | | | | | | | | | | | | | | | Ensure CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX depends on CONFIG_COMMON_CLK to fix the following link errors when compile testing some random kernel configurations: m68k-linux-ld: drivers/phy/rockchip/phy-rockchip-samsung-hdptx.o: in function `rk_hdptx_phy_clk_register': drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c:1031:(.text+0x470): undefined reference to `__clk_get_name' m68k-linux-ld: drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c:1036:(.text+0x4ba): undefined reference to `devm_clk_hw_register' m68k-linux-ld: drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c:1040:(.text+0x4d2): undefined reference to `of_clk_hw_simple_get' m68k-linux-ld: drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c:1040:(.text+0x4da): undefined reference to `devm_of_clk_add_hw_provider' Fixes: c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock provider support") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202409180305.53PXymZn-lkp@intel.com/ Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240923-sam-hdptx-link-fix-v1-1-8d10d7456305@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: phy-rockchip-samsung-hdptx: Add clock provider supportCristian Ciocaltea2024-08-051-22/+173
| | | | | | | | | | | | | | The HDMI PHY PLL can be used as an alternative dclk source to RK3588 SoC CRU. It provides more accurate clock rates required by VOP2 to improve existing support for display modes handling, which is known to be problematic when dealing with non-integer refresh rates, among others. It is worth noting this only works for HDMI 2.0 or below, e.g. cannot be used to support HDMI 2.1 4K@120Hz mode. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20240620-rk3588-hdmiphy-clkprov-v2-4-6a2d2164e508@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: phy-rockchip-samsung-hdptx: Enable runtime PM at PHY core levelCristian Ciocaltea2024-08-051-18/+6
| | | | | | | | | | | | | | | | | | | | | | When a new PHY is created via [devm_]phy_create(), the runtime PM for it is not enabled unless the parent device (which creates the PHY) has its own runtime PM already enabled. Move the call to devm_pm_runtime_enable() before devm_phy_create() to enable runtime PM at PHY core level. With this change the ->power_on() and ->power_off() callbacks do not require explicit runtime PM management anymore, since the PHY core handles that via phy_pm_runtime_{get,put}_sync() when phy_power_on() and phy_power_off() are invoked. Hence drop the now unnecessary calls to pm_runtime_resume_and_get() and pm_runtime_put() helpers. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20240620-rk3588-hdmiphy-clkprov-v2-2-6a2d2164e508@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: phy-rockchip-samsung-hdptx: Explicitly include pm_runtime.hCristian Ciocaltea2024-08-051-0/+1
| | | | | | | | | | | | | | Driver makes use of helpers from pm_runtime.h, but relies on the header file being implicitly included. Explicitly pull the header in to avoid potential build failures in some configurations. Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver") Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20240620-rk3588-hdmiphy-clkprov-v2-1-6a2d2164e508@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: phy-rockchip-samsung-hdptx: Select CONFIG_MFD_SYSCONCristian Ciocaltea2024-07-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Compile testing configurations without REGMAP support enabled results in a bunch of errors being reported: ../drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c:569:21: error: variable ‘rk_hdptx_phy_regmap_config’ has initializer but incomplete type 569 | static const struct regmap_config rk_hdptx_phy_regmap_config = { | ^~~~~~~~~~~~~ ../drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c:570:10: error: ‘const struct regmap_config’ has no member named ‘reg_bits’ 570 | .reg_bits = 32, | ^~~~~~~~ Note that selecting REGMAP alone is not enough, because of the following liker error: phy-rockchip-samsung-hdptx.c:(.text+0x10c): undefined reference to `__devm_regmap_init_mmio_clk' Instead of the obvious fix to enable REGMAP_MMIO, select MFD_SYSCON, which implicitly enables REGMAP_MMIO as well. The rationale is that the driver has been already relying on the syscon functionality. Moreover, without MFD_SYSCON enabled, the test coverage is reduced, since the linker might not detect any potential undefined references following syscon_regmap_lookup_by_phandle() invocation in rk_hdptx_phy_probe() body. That is because the function would unconditionally return -ENOTSUP, hence the compiler is free to optimize out any unreachable code. Finally ensure PHY_ROCKCHIP_SAMSUNG_HDPTX depends on HAS_IOMEM, as required by MFD_SYSCON. Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20240629-rk-hdptx-compile-test-fix-v1-1-c86675ba8070@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* Merge tag 'phy-for-6.10' of ↵Linus Torvalds2024-05-215-8/+1666
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull generic phy updates from Vinod Koul: "New HW Support: - Support for Embedded DisplayPort and DisplayPort submodes and driver support on Qualcomm X1E80100 edp driver - Qualcomm QMP UFS PHY for SM8475, QMP USB phy for QDU1000/QRU1000 and eusb2-repeater for SMB2360 - Samsung HDMI PHY for i.MX8MP, gs101 UFS phy - Mediatek XFI T-PHY support for mt7988 - Rockchip usbdp combo phy driver Updates: - Qualcomm x4 lane EP support for sa8775p, v4 ad v6 support for X1E80100, SM8650 tables for UFS Gear 4 & 5 and correct voltage swing tables - Freescale imx8m-pci pcie link-up updates - Rockchip rx-common-refclk-mode support - More platform remove callback returning void conversions" * tag 'phy-for-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (43 commits) dt-bindings: phy: qcom,usb-snps-femto-v2: use correct fallback for sc8180x dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: fix msm899[68] power-domains dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: fix x1e80100-gen3x2 schema phy: qcpm-qmp-usb: Add support for QDU1000/QRU1000 dt-bindings: phy: qcom,qmp-usb: Add QDU1000 USB3 PHY dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for QDU1000 phy: qcom-qmp-pcie: add x4 lane EP support for sa8775p phy: samsung-ufs: ufs: exit on first reported error phy: samsung-ufs: ufs: remove superfluous mfd/syscon.h header phy: rockchip: fix CONFIG_TYPEC dependency phy: rockchip: usbdp: fix uninitialized variable phy: rockchip-snps-pcie3: add support for rockchip,rx-common-refclk-mode dt-bindings: phy: rockchip,pcie3-phy: add rockchip,rx-common-refclk-mode phy: rockchip: add usbdp combo phy driver dt-bindings: phy: add rockchip usbdp combo phy document phy: add driver for MediaTek XFI T-PHY dt-bindings: phy: mediatek,mt7988-xfi-tphy: add new bindings phy: freescale: fsl-samsung-hdmi: Convert to platform remove callback returning void phy: qcom: qmp-ufs: update SM8650 tables for Gear 4 & 5 MAINTAINERS: Add phy-gs101-ufs file to Tensor GS101. ...
| * phy: rockchip: fix CONFIG_TYPEC dependencyArnd Bergmann2024-04-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The newly added driver causes a warning about missing dependencies by selecting CONFIG_TYPEC unconditionally: WARNING: unmet direct dependencies detected for TYPEC Depends on [n]: USB_SUPPORT [=n] Selected by [y]: - PHY_ROCKCHIP_USBDP [=y] && ARCH_ROCKCHIP [=y] && OF [=y] WARNING: unmet direct dependencies detected for USB_COMMON Depends on [n]: USB_SUPPORT [=n] Selected by [y]: - EXTCON_RTK_TYPE_C [=y] && EXTCON [=y] && (ARCH_REALTEK [=y] || COMPILE_TEST [=y]) && TYPEC [=y] Since that is a user-visible option, it should not really be selected in the first place. Replace the 'select' with a 'depends on' as we have for similar drivers. Fixes: 2f70bbddeb45 ("phy: rockchip: add usbdp combo phy driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240415174241.77982-1-arnd@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: rockchip: usbdp: fix uninitialized variableSebastian Reichel2024-04-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ret variable may not be initialized in rk_udphy_usb3_phy_init(), if the PHY is not using USB3 mode. Since the DisplayPort part is handled separately and the PHY does not support USB2 (which is routed to another PHY on Rockchip RK3588), the right exit code for this case is 0. Thus let's initialize the variable accordingly. Fixes: 2f70bbddeb457 ("phy: rockchip: add usbdp combo phy driver") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202404141048.qFAYDctQ-lkp@intel.com/ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Reviewed-by: Muhammad Usama Anjum <usama.anjum@collabora.com> Link: https://lore.kernel.org/r/20240416145233.94687-1-sebastian.reichel@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: rockchip-snps-pcie3: add support for rockchip,rx-common-refclk-modeNiklas Cassel2024-04-131-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | >From the RK3588 Technical Reference Manual, Part1, section 6.19 PCIe3PHY_GRF Register Description: "rxX_cmn_refclk_mode" RX common reference clock mode for lane X. This mode should be enabled only when the far-end and near-end devices are running with a common reference clock. The hardware reset value for this field is 0x1 (enabled). Note that this register field is only available on RK3588, not on RK3568. The link training either fails or is highly unstable (link state will jump continuously between L0 and recovery) when this mode is enabled while using an endpoint running in Separate Reference Clock with No SSC (SRNS) mode or Separate Reference Clock with SSC (SRIS) mode. (Which is usually the case when using a real SoC as endpoint, e.g. the RK3588 PCIe controller can run in both Root Complex and Endpoint mode.) Add support for the device tree property rockchip,rx-common-refclk-mode, such that the PCIe PHY can be used in configurations where the Root Complex and Endpoint are not using a common reference clock. Signed-off-by: Niklas Cassel <cassel@kernel.org> Link: https://lore.kernel.org/r/20240412125818.17052-3-cassel@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * phy: rockchip: add usbdp combo phy driverSebastian Reichel2024-04-123-0/+1621
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a new USBDP combo PHY with Samsung IP block driver. The driver get lane mux and mapping info in 2 ways, supporting DisplayPort alternate mode or parsing from DT. When parsing from DT, the property "rockchip,dp-lane-mux" provide the DP mux and mapping info. This is needed when the PHY is not used with TypeC Alt-Mode. For example if the USB3 interface of the PHY is connected to a USB Type A connector and the DP interface is connected to a DisplayPort connector. When do DP link training, need to set lane number, link rate, swing, and pre-emphasis via PHY configure interface. Co-developed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Co-developed-by: Zhang Yubing <yubing.zhang@rock-chips.com> Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com> Co-developed-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20240408225109.128953-3-sebastian.reichel@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * Merge branch 'fixes' into nextVinod Koul2024-04-122-21/+46
| |\ | | | | | | | | | | | | This brings rockchip,pcie3-phy changes into next which incoming patches are dependent on
| * | phy: rockchip: Fix typo in function namesRick Wertenbroek2024-04-052-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several functions had "rochchip" instead of "rockchip" in their name. Replace "rochchip" by "rockchip". Signed-off-By: Rick Wertenbroek <rick.wertenbroek@gmail.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240307095318.3651498-1-rick.wertenbroek@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | | phy: phy-rockchip-samsung-hdptx: Select CONFIG_RATIONALCristian Ciocaltea2024-04-121-0/+1
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ensure CONFIG_RATIONAL is selected in order to fix the following link error with some kernel configurations: drivers/phy/rockchip/phy-rockchip-samsung-hdptx.o: in function `rk_hdptx_ropll_tmds_cmn_config': phy-rockchip-samsung-hdptx.c:(.text+0x950): undefined reference to `rational_best_approximation' Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202404090540.2l1TEkDF-lkp@intel.com/ Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240408222926.32708-1-cristian.ciocaltea@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: rockchip: naneng-combphy: Fix mux on rk3588Sebastian Reichel2024-04-061-3/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pcie1l0_sel and pcie1l1_sel bits in PCIESEL_CON configure the mux for PCIe1L0 and PCIe1L1 to either the PIPE Combo PHYs or the PCIe3 PHY. Thus this configuration interfers with the data-lanes configuration done by the PCIe3 PHY. RK3588 has three Combo PHYs. The first one has a dedicated PCIe controller and is not affected by this. For the other two Combo PHYs, there is one mux for each of them. pcie1l0_sel selects if PCIe 1L0 is muxed to Combo PHY 1 when bit is set to 0 or to the PCIe3 PHY when bit is set to 1. pcie1l1_sel selects if PCIe 1L1 is muxed to Combo PHY 2 when bit is set to 0 or to the PCIe3 PHY when bit is set to 1. Currently the code always muxes 1L0 and 1L1 to the Combi PHYs once one of them is being used in PCIe mode. This is obviously wrong when at least one of the ports should be muxed to the PCIe3 PHY. Fix this by introducing Combo PHY identification and then only setting up the required bit. Fixes: a03c44277253 ("phy: rockchip: Add naneng combo phy support for RK3588") Reported-by: Michal Tomek <mtdev79b@gmail.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240404-rk3588-pcie-bifurcation-fixes-v1-3-9907136eeafd@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: rockchip-snps-pcie3: fix clearing PHP_GRF_PCIESEL_CON bitsSebastian Reichel2024-04-061-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the PCIe v3 PHY driver only sets the pcie1ln_sel bits, but does not clear them because of an incorrect write mask. This fixes up the issue by using a newly introduced constant for the write mask. While at it also introduces a proper GENMASK based constant for the PCIE30_PHY_MODE. Fixes: 2e9bffc4f713 ("phy: rockchip: Support PCIe v3") Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240404-rk3588-pcie-bifurcation-fixes-v1-2-9907136eeafd@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: rockchip-snps-pcie3: fix bifurcation on rk3588Michal Tomek2024-04-061-16/+8
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far all RK3588 boards use fully aggregated PCIe. CM3588 is one of the few boards using this feature and apparently it is broken. The PHY offers the following mapping options: port 0 lane 0 - always mapped to controller 0 (4L) port 0 lane 1 - to controller 0 or 2 (1L0) port 1 lane 0 - to controller 0 or 1 (2L) port 1 lane 1 - to controller 0, 1 or 3 (1L1) The data-lanes DT property maps these as follows: 0 = no controller (unsupported by the HW) 1 = 4L 2 = 2L 3 = 1L0 4 = 1L1 That allows the following configurations with first column being the mainline data-lane mapping, second column being the downstream name, third column being PCIE3PHY_GRF_CMN_CON0 and PHP_GRF_PCIESEL register values and final column being the user visible lane setup: <1 1 1 1> = AGGREG = [4 0] = x4 (aggregation) <1 1 2 2> = NANBNB = [0 0] = x2 x2 (no bif.) <1 3 2 2> = NANBBI = [1 1] = x2 x1x1 (bif. of port 0) <1 1 2 4> = NABINB = [2 2] = x1x1 x2 (bif. of port 1) <1 3 2 4> = NABIBI = [3 3] = x1x1 x1x1 (bif. of both ports) The driver currently does not program PHP_GRF_PCIESEL correctly, which is fixed by this patch. As a side-effect the new logic is much simpler than the old logic. Fixes: 2e9bffc4f713 ("phy: rockchip: Support PCIe v3") Signed-off-by: Michal Tomek <mtdev79b@gmail.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240404-rk3588-pcie-bifurcation-fixes-v1-1-9907136eeafd@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: constify of_phandle_args in xlateKrzysztof Kozlowski2024-02-232-2/+2
| | | | | | | | | | | | | The xlate callbacks are supposed to translate of_phandle_args to proper provider without modifying the of_phandle_args. Make the argument pointer to const for code safety and readability. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Florian Fainelli <florian.fainelli@broadcom.com> #Broadcom Link: https://lore.kernel.org/r/20240217093937.58234-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: rockchip: Add Samsung HDMI/eDP Combo PHY driverCristian Ciocaltea2024-02-163-0/+1037
| | | | | | | | | | | | | | | | | Add driver for the HDMI/eDP TX Combo PHY found on Rockchip RK3588 SoC. The PHY is based on a Samsung IP block and supports HDMI 2.1 TMDS, FRL and eDP links. The maximum data rate is 12Gbps (FRL), while the minimum is 250Mbps (TMDS). Only the TMDS link is currently supported. Co-developed-by: Algea Cao <algea.cao@rock-chips.com> Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20240214-phy-hdptx-v4-2-e7974f46c1a7@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: phy-rockchip-inno-usb2: Add RK3128 supportAlex Bee2023-11-271-0/+57
| | | | | | | | | Add registers to support the 2-port usb2 phy found in RK312x SoC familiy. Signed-off-by: Alex Bee <knaerzche@gmail.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20231119121340.109025-3-knaerzche@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: rockchip-inno-usb2: Split ID interrupt phy registersAlex Bee2023-11-271-29/+70
| | | | | | | | | | | | | | | | | | | | | Commit 51a9b2c03dd3 ("phy: rockchip-inno-usb2: Handle ID IRQ") added ID detection interrupt registers. However the current implementation assumes that falling and rising edge interrupt are always enabled in registers spanning over subsequent bits. That is not the case for RK3128's version of the phy and this implementation can't be used as-is, since there are bits with different purpose in between. This splits up the register definitions for id_det_en, id_det_en and id_det_clr registers in rising and falling edge variants. It's required as preparation to support RK3128's Innosilicon usb2 phy as well in this driver and matches pretty much to what the vendor does, so I'm not expecting issues for other SoCs with that change. Signed-off-by: Alex Bee <knaerzche@gmail.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20231119121340.109025-2-knaerzche@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: rockchip-inno-usb2: Drop unnecessary DT includesRob Herring2023-10-131-2/+0
| | | | | | | | | Neither of_address.h or of_platform.h are used in the driver, so drop them. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20231009172923.2457844-17-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: Use device_get_match_data()Rob Herring2023-10-132-14/+7
| | | | | | | | | | | Use preferred device_get_match_data() instead of of_match_device() to get the driver match data. With this, adjust the includes to explicitly include the correct headers. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20231009172923.2457844-15-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: rockchip: inno-dsidphy: Add rv1126 supportJagan Teki2023-08-221-0/+3
| | | | | | | | | | | | Add support for Rockchip RV1126 DSI-DPHY. The existing 2.5GHz phy timing table added for RK3568 is working as it is for RV1126 as well. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20230731110012.2913742-5-jagan@edgeble.ai Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: Explicitly include correct DT includesRob Herring2023-07-175-5/+5
| | | | | | | | | | | | | | | | | | The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> # for drivers/phy/phy-can-transceiver.c Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20230714174841.4061919-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy/rockchip: inno-hdmi: add more supported pre-pll ratesAlex Bee2023-07-121-25/+173
| | | | | | | | | | | | | | | | | | | | | | | | | This adds a bunch of new pixel clock- and tmds rates to the pre-pll table which are required to get more VESA and some DMT rates working. It has been completely re-calculated to match the min- and max-vco of (750 MHz - 3.2 GHz) requirements. If more than one configuration would have been possible the lowest fbdiv and refdiv (and therefore lowest vco rate) has been preferred. It's important to note, that RK3228 version of the phy does not support fractional dividers. To support the most possible rates for this version also in both 8-bit and 10-bit variant, some rates are not exact. The maximum deviation of the pixel clock is 0.26, which perfectly fits into VESA DMT recommendation of 0.5%. I tested all possible rates on several screens from different manufacturers with both RK3228 and RK3328. Both pre- and post-PLL locking are slighlty faster now. Signed-off-by: Alex Bee <knaerzche@gmail.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20230615171005.2251032-7-jonas@kwiboo.se Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy/rockchip: inno-hdmi: force set_rate on power_onHuicong Xu2023-07-121-0/+13
| | | | | | | | | | | | | | | | | Regular 8-bit and Deep Color video formats mainly differ in TMDS rate and not in pixel clock rate. When the hdmiphy clock is configured with the same pixel clock rate using clk_set_rate() the clock framework do not signal the hdmi phy driver to set_rate when switching between 8-bit and Deep Color. This result in pre/post pll not being re-configured when switching between regular 8-bit and Deep Color video formats. Fix this by calling set_rate in power_on to force pre pll re-configuration. Signed-off-by: Huicong Xu <xhc@rock-chips.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20230615171005.2251032-6-jonas@kwiboo.se Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy/rockchip: inno-hdmi: do not power on rk3328 post pll on reg writeJonas Karlman2023-07-121-2/+4
| | | | | | | | | | | | | | | inno_write is used to configure 0xaa reg, that also hold the POST_PLL_POWER_DOWN bit. When POST_PLL_REFCLK_SEL_TMDS is configured the power down bit is not taken into consideration. Fix this by keeping the power down bit until configuration is complete. Also reorder the reg write order for consistency. Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20230615171005.2251032-5-jonas@kwiboo.se Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy/rockchip: inno-hdmi: remove unused no_c from rk3328 recalc_rateJonas Karlman2023-07-121-4/+1
| | | | | | | | no_c is not used in any calculation, lets remove it. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20230615171005.2251032-4-jonas@kwiboo.se Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy/rockchip: inno-hdmi: round fractal pixclock in rk3328 recalc_rateZheng Yang2023-07-121-3/+5
| | | | | | | | | | | | | | | | inno_hdmi_phy_rk3328_clk_recalc_rate() is returning a rate not found in the pre pll config table when the fractal divider is used. This can prevent proper power_on because a tmdsclock for the new rate is not found in the pre pll config table. Fix this by saving and returning a rounded pixel rate that exist in the pre pll config table. Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy") Signed-off-by: Zheng Yang <zhengyang@rock-chips.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20230615171005.2251032-3-jonas@kwiboo.se Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy/rockchip: inno-hdmi: use correct vco_div_5 macro on rk3328Jonas Karlman2023-07-121-2/+2
| | | | | | | | | | | | inno_hdmi_phy_rk3328_clk_set_rate() is using the RK3228 macro when configuring vco_div_5 on RK3328. Fix this by using correct vco_div_5 macro for RK3328. Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20230615171005.2251032-2-jonas@kwiboo.se Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: phy-rockchip-inno-usb2: improve error messageSebastian Reichel2023-07-121-2/+1
| | | | | | | | | | Printing the OF node is not useful, since we get the same information from the device context. Instead print the reg address, that could not be found. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20230522170324.61349-8-sebastian.reichel@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: phy-rockchip-inno-usb2: simplify getting match dataSebastian Reichel2023-07-121-8/+4
| | | | | | | | | Simplify the code by directly getting the match data via device_get_match_data() instead of open coding its functionality. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20230522170324.61349-7-sebastian.reichel@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: phy-rockchip-inno-usb2: simplify phy clock handlingSebastian Reichel2023-07-121-13/+6
| | | | | | | | | | Simplify phyclk handling by using devm_clk_get_optional_enabled to acquire and enable the optional clock. This also fixes a resource leak in driver remove path and adds proper error handling. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20230522170324.61349-6-sebastian.reichel@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: phy-rockchip-inno-usb2: add rk3588 phy tuning supportSebastian Reichel2023-07-121-0/+63
| | | | | | | | | | | | | | On RK3588 some registers need to be tweaked to support waking up from suspend when a USB device is plugged into a port from a suspended PHY. Without this change USB devices only work when they are plugged at boot time. Apart from that it optimizes settings to avoid devices toggling between fullspeed and highspeed mode. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20230522170324.61349-5-sebastian.reichel@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: phy-rockchip-inno-usb2: add reset supportSebastian Reichel2023-07-121-0/+38
| | | | | | | | | Add reset handling support, which is needed for proper operation with RK3588. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20230522170324.61349-4-sebastian.reichel@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: phy-rockchip-inno-usb2: add rk3588 supportSebastian Reichel2023-07-121-15/+211
| | | | | | | | | | Add basic support for the USB2 PHY found in the Rockchip RK3588. Co-developed-by: William Wu <william.wu@rock-chips.com> Signed-off-by: William Wu <william.wu@rock-chips.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20230522170324.61349-3-sebastian.reichel@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: rockchip: phy-rockchip-typec: Use devm_platform_get_and_ioremap_resource()Yangtao Li2023-07-121-2/+1
| | | | | | | | | | Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li <frank.li@vivo.com> Link: https://lore.kernel.org/r/20230705090126.26854-2-frank.li@vivo.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: rockchip: remove unused hw_to_inno functionTom Rix2023-04-121-5/+0
| | | | | | | | | | | | | | clang with W=1 reports drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c:284:36: error: unused function 'hw_to_inno' [-Werror,-Wunused-function] static inline struct inno_dsidphy *hw_to_inno(struct clk_hw *hw) ^ This function is not used so remove it. Signed-off-by: Tom Rix <trix@redhat.com> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Link: https://lore.kernel.org/r/20230324132649.2649166-1-trix@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: rockchip: Add naneng combo phy support for RK3588Lucas Tanure2023-03-311-0/+184
| | | | | | | | | | | | | Add support for RK3588 combo phy This is based on prior work from XiaoDong Huang and Peter Geis fixing this issue specifically for Rockchip 356x. Co-developed-by: Andrew Powers-Holmes <aholmes@omnom.net> Signed-off-by: Andrew Powers-Holmes <aholmes@omnom.net> Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com> Link: https://lore.kernel.org/r/20230314135555.44162-4-lucas.tanure@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: rockchip-pcie: remove unused phy_rd_cfg functionTom Rix2023-03-311-15/+0
| | | | | | | | | | | | | clang with W=1 reports drivers/phy/rockchip/phy-rockchip-pcie.c:122:19: error: unused function 'phy_rd_cfg' [-Werror,-Wunused-function] static inline u32 phy_rd_cfg(struct rockchip_pcie_phy *rk_phy, ^ This function is not used, so remove it. Signed-off-by: Tom Rix <trix@redhat.com> Link: https://lore.kernel.org/r/20230321122503.1783311-1-trix@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: rockchip: phy-rockchip-typec: Convert to platform remove callback ↵Uwe Kleine-König2023-03-201-4/+2
| | | | | | | | | | | | | | | | | | | | returning void The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20230307115900.2293120-23-u.kleine-koenig@pengutronix.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-02 16:18:37 +0100