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path: root/sound/soc/codecs/tlv320aic32x4-clk.c (follow)
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* ASoC: tlv320aic32x4: Fix the divide by zeroGuiting Shen2023-08-141-5/+11
* ASoC: tlv320aic32x4: pll: Remove impossible condition in clk_aic32x4_pll_dete...Stephen Boyd2023-06-131-5/+1
* ASoC: tlv320aic32x4: div: Switch to determine_rateMaxime Ripard2023-06-091-6/+7
* ASoC: tlv320aic32x4: pll: Switch to determine_rateMaxime Ripard2023-06-091-7/+12
* ASoC: tlv320aic32x4: Add a determine_rate hookMaxime Ripard2023-06-091-0/+1
* ASoC: tlv320aic32x4: Ensure a minimum delay before clock stabilizationMiquel Raynal2020-09-211-1/+8
* ASoC: tlv320aic32x4: Fix potential uninitialized variableAnnaliese McDermond2019-05-021-1/+1
* ASoC: tlv320aic32x4: Fix spacingAnnaliese McDermond2019-04-081-2/+2
* ASoC: tlv320aic32x4: Model BDIV divider in CCFAnnaliese McDermond2019-03-251-0/+36
* ASoC: tlv320aic32x4: Model DAC/ADC dividers in CCFAnnaliese McDermond2019-03-251-0/+90
* ASoC: tlv320aic32x4: Model CODEC_CLKIN in CCFAnnaliese McDermond2019-03-251-0/+34
* ASoC: tlv320aic32x4: Model PLL in CCFAnnaliese McDermond2019-03-251-0/+323
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