blob: d1b3a95a5518acb056ef315df7ecc6cdda325a74 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
|
What: /sys/devices/platform/HISI04Bx:00/chipX/all_linked
What: /sys/devices/platform/HISI04Bx:00/chipX/linked_full_lane
What: /sys/devices/platform/HISI04Bx:00/chipX/crc_err_cnt
Date: November 2023
KernelVersion: 6.6
Contact: Huisong Li <lihuisong@huawei.com>
Description:
The /sys/devices/platform/HISI04Bx:00/chipX/ directory
contains read-only attributes exposing some summarization
information of all HCCS ports under a specified chip.
The X in 'chipX' indicates the Xth chip on platform.
There are following attributes in this directory:
================= ==== =========================================
all_linked: (RO) if all enabled ports on this chip are
linked (bool).
linked_full_lane: (RO) if all linked ports on this chip are full
lane (bool).
crc_err_cnt: (RO) total CRC err count for all ports on this
chip.
================= ==== =========================================
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/all_linked
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/linked_full_lane
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/crc_err_cnt
Date: November 2023
KernelVersion: 6.6
Contact: Huisong Li <lihuisong@huawei.com>
Description:
The /sys/devices/platform/HISI04Bx:00/chipX/dieY/ directory
contains read-only attributes exposing some summarization
information of all HCCS ports under a specified die.
The Y in 'dieY' indicates the hardware id of the die on chip who
has chip id X.
There are following attributes in this directory:
================= ==== =========================================
all_linked: (RO) if all enabled ports on this die are
linked (bool).
linked_full_lane: (RO) if all linked ports on this die are full
lane (bool).
crc_err_cnt: (RO) total CRC err count for all ports on this
die.
================= ==== =========================================
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/type
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/lane_mode
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/enable
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/cur_lane_num
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/link_fsm
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/lane_mask
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/crc_err_cnt
Date: November 2023
KernelVersion: 6.6
Contact: Huisong Li <lihuisong@huawei.com>
Description:
The /sys/devices/platform/HISI04Bx/chipX/dieX/hccsN/ directory
contains read-only attributes exposing information about
a HCCS port. The N value in 'hccsN' indicates this port id.
The X in 'chipX' indicates the ID of the chip to which the
HCCS port belongs. For example, X ranges from to 'n - 1' if the
chip number on platform is n.
The Y in 'dieY' indicates the hardware id of the die to which
the hccs port belongs.
Note: type, lane_mode and enable are fixed attributes on running
platform.
The HCCS port have the following attributes:
============= ==== =============================================
type: (RO) port type (string), e.g. HCCS-v1 -> H32
lane_mode: (RO) the lane mode of this port (string), e.g. x8
enable: (RO) indicate if this port is enabled (bool).
cur_lane_num: (RO) current lane number of this port.
link_fsm: (RO) link finite state machine of this port.
lane_mask: (RO) current lane mask of this port, every bit
indicates a lane.
crc_err_cnt: (RO) CRC err count on this port.
============= ==== =============================================
What: /sys/devices/platform/HISI04Bx:00/used_types
Date: August 2024
KernelVersion: 6.12
Contact: Huisong Li <lihuisong@huawei.com>
Description:
This interface is used to show all HCCS types used on the
platform, like, HCCS-v1, HCCS-v2 and so on.
What: /sys/devices/platform/HISI04Bx:00/available_inc_dec_lane_types
What: /sys/devices/platform/HISI04Bx:00/dec_lane_of_type
What: /sys/devices/platform/HISI04Bx:00/inc_lane_of_type
Date: August 2024
KernelVersion: 6.12
Contact: Huisong Li <lihuisong@huawei.com>
Description:
These interfaces under /sys/devices/platform/HISI04Bx/ are
used to support the low power consumption feature of some
HCCS types by changing the number of lanes used. The interfaces
changing the number of lanes used are 'dec_lane_of_type' and
'inc_lane_of_type' which require root privileges. These
interfaces aren't exposed if no HCCS type on platform support
this feature. Please note that decreasing lane number is only
allowed if all the specified HCCS ports are not busy.
The low power consumption interfaces are as follows:
============================= ==== ================================
available_inc_dec_lane_types: (RO) available HCCS types (string) to
increase and decrease the number
of lane used, e.g. HCCS-v2.
dec_lane_of_type: (WO) input HCCS type supported
decreasing lane to decrease the
used lane number of all specified
HCCS type ports on platform to
the minimum.
You can query the 'cur_lane_num'
to get the minimum lane number
after executing successfully.
inc_lane_of_type: (WO) input HCCS type supported
increasing lane to increase the
used lane number of all specified
HCCS type ports on platform to
the full lane state.
============================= ==== ================================
|
