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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,qcm2290-gpucc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller on QCM2290
maintainers:
- Konrad Dybcio <konradybcio@kernel.org>
description: |
Qualcomm graphics clock control module provides the clocks, resets and power
domains on Qualcomm SoCs.
See also::
include/dt-bindings/clock/qcom,qcm2290-gpucc.h
properties:
compatible:
const: qcom,qcm2290-gpucc
reg:
maxItems: 1
clocks:
items:
- description: AHB interface clock,
- description: SoC CXO clock
- description: GPLL0 main branch source
- description: GPLL0 div branch source
power-domains:
description:
A phandle and PM domain specifier for the CX power domain.
maxItems: 1
required-opps:
description:
A phandle to an OPP node describing required CX performance point.
maxItems: 1
required:
- compatible
- clocks
- power-domains
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-qcm2290.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@5990000 {
compatible = "qcom,qcm2290-gpucc";
reg = <0x0 0x05990000 0x0 0x9000>;
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
power-domains = <&rpmpd QCM2290_VDDCX>;
required-opps = <&rpmpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
};
...
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