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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright (C) 2022 Renesas Electronics Corp.
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/renesas,rzg2l-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/G2L (and alike SoC's) Camera Data Receiving Unit (CRU) Image processing
maintainers:
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
description:
The CRU image processing module is a data conversion module equipped with pixel
color space conversion, LUT, pixel format conversion, etc. An MIPI CSI-2 input and
parallel (including ITU-R BT.656) input are provided as the image sensor interface.
properties:
compatible:
items:
- enum:
- renesas,r9a07g044-cru # RZ/G2{L,LC}
- renesas,r9a07g054-cru # RZ/V2L
- const: renesas,rzg2l-cru
reg:
maxItems: 1
interrupts:
maxItems: 3
interrupt-names:
items:
- const: image_conv
- const: image_conv_err
- const: axi_mst_err
clocks:
items:
- description: CRU Main clock
- description: CRU Register access clock
- description: CRU image transfer clock
clock-names:
items:
- const: video
- const: apb
- const: axi
power-domains:
maxItems: 1
resets:
items:
- description: CRU_PRESETN reset terminal
- description: CRU_ARESETN reset terminal
reset-names:
items:
- const: presetn
- const: aresetn
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description:
Input port node, single endpoint describing a parallel input source.
properties:
endpoint:
$ref: video-interfaces.yaml#
unevaluatedProperties: false
properties:
hsync-active: true
vsync-active: true
bus-width: true
data-shift: true
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
Input port node, describing the Image Processing module connected to the
CSI-2 receiver.
required:
- port@0
- port@1
required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
- clock-names
- resets
- reset-names
- power-domains
additionalProperties: false
examples:
# Device node example with CSI-2
- |
#include <dt-bindings/clock/r9a07g044-cpg.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
cru: video@10830000 {
compatible = "renesas,r9a07g044-cru", "renesas,rzg2l-cru";
reg = <0x10830000 0x400>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "image_conv", "image_conv_err", "axi_mst_err";
clocks = <&cpg CPG_MOD R9A07G044_CRU_VCLK>,
<&cpg CPG_MOD R9A07G044_CRU_PCLK>,
<&cpg CPG_MOD R9A07G044_CRU_ACLK>;
clock-names = "video", "apb", "axi";
power-domains = <&cpg>;
resets = <&cpg R9A07G044_CRU_PRESETN>,
<&cpg R9A07G044_CRU_ARESETN>;
reset-names = "presetn", "aresetn";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
cru_parallel_in: endpoint@0 {
reg = <0>;
remote-endpoint= <&ov5642>;
hsync-active = <1>;
vsync-active = <1>;
};
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
cru_csi_in: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi_cru_in>;
};
};
};
};
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