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Xilinx Video Test Pattern Generator (TPG)
-----------------------------------------
Required properties:
- compatible: Must contain at least one of
"xlnx,v-tpg-5.0" (TPG version 5.0)
"xlnx,v-tpg-6.0" (TPG version 6.0)
TPG versions backward-compatible with previous versions should list all
compatible versions in the newer to older order.
- reg: Physical base address and length of the registers set for the device.
- clocks: Reference to the video core clock.
- xlnx,video-format, xlnx,video-width: Video format and width, as defined in
video.txt.
- port: Video port, using the DT bindings defined in ../video-interfaces.txt.
The TPG has a single output port numbered 0.
Optional properties:
- xlnx,vtc: A phandle referencing the Video Timing Controller that generates
video timings for the TPG test patterns.
- timing-gpios: Specifier for a GPIO that controls the timing mux at the TPG
input. The GPIO active level corresponds to the selection of VTC-generated
video timings.
The xlnx,vtc and timing-gpios properties are mandatory when the TPG is
synthesized with two ports and forbidden when synthesized with one port.
Example:
tpg_0: tpg@40050000 {
compatible = "xlnx,v-tpg-6.0", "xlnx,v-tpg-5.0";
reg = <0x40050000 0x10000>;
clocks = <&clkc 15>;
xlnx,vtc = <&vtc_3>;
timing-gpios = <&ps7_gpio_0 55 GPIO_ACTIVE_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
xlnx,video-format = <XVIP_VF_YUV_422>;
xlnx,video-width = <8>;
tpg_in: endpoint {
remote-endpoint = <&adv7611_out>;
};
};
port@1 {
reg = <1>;
xlnx,video-format = <XVIP_VF_YUV_422>;
xlnx,video-width = <8>;
tpg1_out: endpoint {
remote-endpoint = <&switch_in0>;
};
};
};
};
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