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# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
# Copyright (C) 2019 Texas Instruments Incorporated
%YAML 1.2
---
$id: "http://devicetree.org/schemas/net/ti,dp83867.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: TI DP83867 ethernet PHY
allOf:
- $ref: "ethernet-controller.yaml#"
maintainers:
- Dan Murphy <dmurphy@ti.com>
description: |
The DP83867 device is a robust, low power, fully featured Physical Layer
transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
and 1000BASE-T Ethernet protocols.
The DP83867 is designed for easy implementation of 10/100/1000 Mbps Ethernet
LANs. It interfaces directly to twisted pair media via an external
transformer. This device interfaces directly to the MAC layer through the
IEEE 802.3 Standard Media Independent Interface (MII), the IEEE 802.3 Gigabit
Media Independent Interface (GMII) or Reduced GMII (RGMII).
Specifications about the Ethernet PHY can be found at:
https://www.ti.com/lit/gpn/dp83867ir
properties:
reg:
maxItems: 1
ti,min-output-impedance:
type: boolean
description: |
MAC Interface Impedance control to set the programmable output impedance
to a minimum value (35 ohms).
ti,max-output-impedance:
type: boolean
description: |
MAC Interface Impedance control to set the programmable output impedance
to a maximum value (70 ohms).
Note: ti,min-output-impedance and ti,max-output-impedance are mutually
exclusive. When both properties are present ti,max-output-impedance
takes precedence.
tx-fifo-depth:
$ref: /schemas/types.yaml#definitions/uint32
description: |
Transmitt FIFO depth see dt-bindings/net/ti-dp83867.h for values
rx-fifo-depth:
$ref: /schemas/types.yaml#definitions/uint32
description: |
Receive FIFO depth see dt-bindings/net/ti-dp83867.h for values
ti,clk-output-sel:
$ref: /schemas/types.yaml#definitions/uint32
description: |
Muxing option for CLK_OUT pin. See dt-bindings/net/ti-dp83867.h
for applicable values. The CLK_OUT pin can also be disabled by this
property. When omitted, the PHY's default will be left as is.
ti,rx-internal-delay:
$ref: /schemas/types.yaml#definitions/uint32
description: |
RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
for applicable values. Required only if interface type is
PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID.
ti,tx-internal-delay:
$ref: /schemas/types.yaml#definitions/uint32
description: |
RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
for applicable values. Required only if interface type is
PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID.
Note: If the interface type is PHY_INTERFACE_MODE_RGMII the TX/RX clock
delays will be left at their default values, as set by the PHY's pin
strapping. The default strapping will use a delay of 2.00 ns. Thus
PHY_INTERFACE_MODE_RGMII, by default, does not behave as RGMII with no
internal delay, but as PHY_INTERFACE_MODE_RGMII_ID. The device tree
should use "rgmii-id" if internal delays are desired as this may be
changed in future to cause "rgmii" mode to disable delays.
ti,dp83867-rxctrl-strap-quirk:
type: boolean
description: |
This denotes the fact that the board has RX_DV/RX_CTRL pin strapped in
mode 1 or 2. To ensure PHY operation, there are specific actions that
software needs to take when this pin is strapped in these modes.
See data manual for details.
ti,sgmii-ref-clock-output-enable:
type: boolean
description: |
This denotes which SGMII configuration is used (4 or 6-wire modes).
Some MACs work with differential SGMII clock. See data manual for details.
ti,fifo-depth:
deprecated: true
$ref: /schemas/types.yaml#definitions/uint32
description: |
Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h for applicable
values.
required:
- reg
examples:
- |
#include <dt-bindings/net/ti-dp83867.h>
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
reg = <0>;
tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,max-output-impedance;
ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_RCLK>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
};
};
|
