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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8909-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. MSM8909 TLMM block
maintainers:
- Stephan Gerhold <stephan@gerhold.net>
description: |
Top Level Mode Multiplexer pin controller in Qualcomm MSM8909 SoC.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,msm8909-tlmm
reg:
maxItems: 1
interrupts: true
interrupt-controller: true
"#interrupt-cells": true
gpio-controller: true
gpio-reserved-ranges: true
"#gpio-cells": true
gpio-ranges: true
wakeup-parent: true
required:
- compatible
- reg
additionalProperties: false
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-msm8909-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-msm8909-tlmm-state"
additionalProperties: false
$defs:
qcom-msm8909-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-7])$"
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0, qdsd_data1,
qdsd_data2, qdsd_data3 ]
minItems: 1
maxItems: 16
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ adsp_ext, atest_bbrx0, atest_bbrx1, atest_char, atest_char0,
atest_char1, atest_char2, atest_char3, atest_combodac,
atest_gpsadc0, atest_gpsadc1, atest_wlan0, atest_wlan1,
bimc_dte0, bimc_dte1, blsp_i2c1, blsp_i2c2, blsp_i2c3,
blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_spi1, blsp_spi1_cs1,
blsp_spi1_cs2, blsp_spi1_cs3, blsp_spi2, blsp_spi2_cs1,
blsp_spi2_cs2, blsp_spi2_cs3, blsp_spi3, blsp_spi3_cs1,
blsp_spi3_cs2, blsp_spi3_cs3, blsp_spi4, blsp_spi5, blsp_spi6,
blsp_uart1, blsp_uart2, blsp_uim1, blsp_uim2, cam_mclk,
cci_async, cci_timer0, cci_timer1, cci_timer2, cdc_pdm0,
dbg_out, dmic0_clk, dmic0_data, ebi0_wrcdc, ebi2_a, ebi2_lcd,
ext_lpass, gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a,
gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest, gpio,
gsm0_tx, ldo_en, ldo_update, m_voc, mdp_vsync, modem_tsync,
nav_pps, nav_tsync, pa_indicator, pbs0, pbs1, pbs2,
pri_mi2s_data0_a, pri_mi2s_data0_b, pri_mi2s_data1_a,
pri_mi2s_data1_b, pri_mi2s_mclk_a, pri_mi2s_mclk_b,
pri_mi2s_sck_a, pri_mi2s_sck_b, pri_mi2s_ws_a, pri_mi2s_ws_b,
prng_rosc, pwr_crypto_enabled_a, pwr_crypto_enabled_b,
pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a,
pwr_nav_enabled_b, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,
qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_tracectl_a,
qdss_tracedata_a, qdss_tracedata_b, sd_write, sec_mi2s,
smb_int, ssbi0, ssbi1, uim1_clk, uim1_data, uim1_present,
uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
uim3_clk, uim3_data, uim3_present, uim3_reset, uim_batt,
wcss_bt, wcss_fm, wcss_wlan ]
bias-disable: true
bias-pull-down: true
bias-pull-up: true
drive-strength: true
input-enable: true
output-high: true
output-low: true
required:
- pins
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl@1000000 {
compatible = "qcom,msm8909-tlmm";
reg = <0x1000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 117>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-wo-subnode-state {
pins = "gpio1";
function = "gpio";
};
uart-w-subnodes-state {
rx-pins {
pins = "gpio4";
function = "blsp_uart1";
bias-pull-up;
};
tx-pins {
pins = "gpio5";
function = "blsp_uart1";
bias-disable;
};
};
};
...
|
