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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pwm/renesas,pwm-rcar.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas R-Car PWM Timer Controller
maintainers:
- Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
properties:
compatible:
items:
- enum:
- renesas,pwm-r8a7743 # RZ/G1M
- renesas,pwm-r8a7744 # RZ/G1N
- renesas,pwm-r8a7745 # RZ/G1E
- renesas,pwm-r8a77470 # RZ/G1C
- renesas,pwm-r8a774a1 # RZ/G2M
- renesas,pwm-r8a774b1 # RZ/G2N
- renesas,pwm-r8a774c0 # RZ/G2E
- renesas,pwm-r8a7778 # R-Car M1A
- renesas,pwm-r8a7779 # R-Car H1
- renesas,pwm-r8a7790 # R-Car H2
- renesas,pwm-r8a7791 # R-Car M2-W
- renesas,pwm-r8a7794 # R-Car E2
- renesas,pwm-r8a7795 # R-Car H3
- renesas,pwm-r8a7796 # R-Car M3-W
- renesas,pwm-r8a77965 # R-Car M3-N
- renesas,pwm-r8a77970 # R-Car V3M
- renesas,pwm-r8a77980 # R-Car V3H
- renesas,pwm-r8a77990 # R-Car E3
- renesas,pwm-r8a77995 # R-Car D3
- const: renesas,pwm-rcar
reg:
# base address and length of the registers block for the PWM.
maxItems: 1
'#pwm-cells':
# should be 2. See pwm.yaml in this directory for a description of
# the cells format.
const: 2
clocks:
# clock phandle and specifier pair.
maxItems: 1
power-domains:
maxItems: 1
resets:
maxItems: 1
required:
- compatible
- reg
- '#pwm-cells'
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/r8a7743-cpg-mssr.h>
#include <dt-bindings/power/r8a7743-sysc.h>
pwm0: pwm@e6e30000 {
compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar";
reg = <0xe6e30000 0x8>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 523>;
#pwm-cells = <2>;
pinctrl-0 = <&pwm0_pins>;
pinctrl-names = "default";
};
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