blob: e143b9929763a12024034e6c9184c42967bade17 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
|
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
/*
* Copyright (C) 2020 huangzhenwei@allwinnertech.com
* Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
*/
#ifndef _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
#define _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
#define CLK_PLL_CPUX 0
#define CLK_PLL_DDR0 1
#define CLK_PLL_PERIPH0_4X 2
#define CLK_PLL_PERIPH0_2X 3
#define CLK_PLL_PERIPH0_800M 4
#define CLK_PLL_PERIPH0 5
#define CLK_PLL_PERIPH0_DIV3 6
#define CLK_PLL_VIDEO0_4X 7
#define CLK_PLL_VIDEO0_2X 8
#define CLK_PLL_VIDEO0 9
#define CLK_PLL_VIDEO1_4X 10
#define CLK_PLL_VIDEO1_2X 11
#define CLK_PLL_VIDEO1 12
#define CLK_PLL_VE 13
#define CLK_PLL_AUDIO0_4X 14
#define CLK_PLL_AUDIO0_2X 15
#define CLK_PLL_AUDIO0 16
#define CLK_PLL_AUDIO1 17
#define CLK_PLL_AUDIO1_DIV2 18
#define CLK_PLL_AUDIO1_DIV5 19
#define CLK_CPUX 20
#define CLK_CPUX_AXI 21
#define CLK_CPUX_APB 22
#define CLK_PSI_AHB 23
#define CLK_APB0 24
#define CLK_APB1 25
#define CLK_MBUS 26
#define CLK_DE 27
#define CLK_BUS_DE 28
#define CLK_DI 29
#define CLK_BUS_DI 30
#define CLK_G2D 31
#define CLK_BUS_G2D 32
#define CLK_CE 33
#define CLK_BUS_CE 34
#define CLK_VE 35
#define CLK_BUS_VE 36
#define CLK_BUS_DMA 37
#define CLK_BUS_MSGBOX0 38
#define CLK_BUS_MSGBOX1 39
#define CLK_BUS_MSGBOX2 40
#define CLK_BUS_SPINLOCK 41
#define CLK_BUS_HSTIMER 42
#define CLK_AVS 43
#define CLK_BUS_DBG 44
#define CLK_BUS_PWM 45
#define CLK_BUS_IOMMU 46
#define CLK_DRAM 47
#define CLK_MBUS_DMA 48
#define CLK_MBUS_VE 49
#define CLK_MBUS_CE 50
#define CLK_MBUS_TVIN 51
#define CLK_MBUS_CSI 52
#define CLK_MBUS_G2D 53
#define CLK_MBUS_RISCV 54
#define CLK_BUS_DRAM 55
#define CLK_MMC0 56
#define CLK_MMC1 57
#define CLK_MMC2 58
#define CLK_BUS_MMC0 59
#define CLK_BUS_MMC1 60
#define CLK_BUS_MMC2 61
#define CLK_BUS_UART0 62
#define CLK_BUS_UART1 63
#define CLK_BUS_UART2 64
#define CLK_BUS_UART3 65
#define CLK_BUS_UART4 66
#define CLK_BUS_UART5 67
#define CLK_BUS_I2C0 68
#define CLK_BUS_I2C1 69
#define CLK_BUS_I2C2 70
#define CLK_BUS_I2C3 71
#define CLK_SPI0 72
#define CLK_SPI1 73
#define CLK_BUS_SPI0 74
#define CLK_BUS_SPI1 75
#define CLK_EMAC_25M 76
#define CLK_BUS_EMAC 77
#define CLK_IR_TX 78
#define CLK_BUS_IR_TX 79
#define CLK_BUS_GPADC 80
#define CLK_BUS_THS 81
#define CLK_I2S0 82
#define CLK_I2S1 83
#define CLK_I2S2 84
#define CLK_I2S2_ASRC 85
#define CLK_BUS_I2S0 86
#define CLK_BUS_I2S1 87
#define CLK_BUS_I2S2 88
#define CLK_SPDIF_TX 89
#define CLK_SPDIF_RX 90
#define CLK_BUS_SPDIF 91
#define CLK_DMIC 92
#define CLK_BUS_DMIC 93
#define CLK_AUDIO_DAC 94
#define CLK_AUDIO_ADC 95
#define CLK_BUS_AUDIO 96
#define CLK_USB_OHCI0 97
#define CLK_USB_OHCI1 98
#define CLK_BUS_OHCI0 99
#define CLK_BUS_OHCI1 100
#define CLK_BUS_EHCI0 101
#define CLK_BUS_EHCI1 102
#define CLK_BUS_OTG 103
#define CLK_BUS_LRADC 104
#define CLK_BUS_DPSS_TOP 105
#define CLK_HDMI_24M 106
#define CLK_HDMI_CEC_32K 107
#define CLK_HDMI_CEC 108
#define CLK_BUS_HDMI 109
#define CLK_MIPI_DSI 110
#define CLK_BUS_MIPI_DSI 111
#define CLK_TCON_LCD0 112
#define CLK_BUS_TCON_LCD0 113
#define CLK_TCON_TV 114
#define CLK_BUS_TCON_TV 115
#define CLK_TVE 116
#define CLK_BUS_TVE_TOP 117
#define CLK_BUS_TVE 118
#define CLK_TVD 119
#define CLK_BUS_TVD_TOP 120
#define CLK_BUS_TVD 121
#define CLK_LEDC 122
#define CLK_BUS_LEDC 123
#define CLK_CSI_TOP 124
#define CLK_CSI_MCLK 125
#define CLK_BUS_CSI 126
#define CLK_TPADC 127
#define CLK_BUS_TPADC 128
#define CLK_BUS_TZMA 129
#define CLK_DSP 130
#define CLK_BUS_DSP_CFG 131
#define CLK_RISCV 132
#define CLK_RISCV_AXI 133
#define CLK_BUS_RISCV_CFG 134
#define CLK_FANOUT_24M 135
#define CLK_FANOUT_12M 136
#define CLK_FANOUT_16M 137
#define CLK_FANOUT_25M 138
#define CLK_FANOUT_32K 139
#define CLK_FANOUT_27M 140
#define CLK_FANOUT_PCLK 141
#define CLK_FANOUT0 142
#define CLK_FANOUT1 143
#define CLK_FANOUT2 144
#define CLK_BUS_CAN0 145
#define CLK_BUS_CAN1 146
#endif /* _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ */
|
